USRE37427EExpiredUtility
Dynamic type memory
Est. expirySep 22, 2014(expired)· nominal 20-yr term from priority
G11C 5/025G11C 7/10G11C 7/1006G11C 11/34G11C 11/4093G11C 7/06G11C 7/1012G11C 11/4096
40
PatentIndex Score
2
Cited by
9
References
120
Claims
Abstract
In a dynamic type memory, a memory cell array is divided into a plurality of sub arrays on a memory chip. Each of the sub arrays is provided with a data line formed in parallel with word lines. Data buffer and multiplexer circuits and I/O pads are arranged on one side of the memory chip in parallel with bit lines. This arrangement allows a data path to be shortened and enables data to be transferred at high speed.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1. A dynamic type memory comprising:
a memory cell array formed on a semiconductor chip having a first edge and a second edge perpendicular to the first edge;
a plurality of sub arrays into which said memory cell array is divided, said plurality of sub arrays being arranged in a first direction parallel to the first edge and a second direction perpendicular to said first direction, and grouped into a plurality of banks, each of said plurality of sub arrays having a plurality of memory cells arranged in matrix;
a plurality of word lines formed on the semiconductor memory chip for each of said plurality of sub arrays and extending in the first direction, each of said plurality of word lines being connected to those of the memory cells which are in a row;
a plurality of bit lines formed on the semiconductor memory chip for each of said plurality of sub arrays and extending in the second direction, each of said plurality of bit lines being connected to those of the memory cells which are in a column;
a plurality of sense amplifiers formed on the semiconductor memory chip for each of said plurality of sub arrays and connected to said plurality of bit lines, each for sensing and amplifying a potential read out from a memory cell when a corresponding bit line is selected;
a plurality of data lines formed on the semiconductor memory chip for said plurality of sub arrays and extending in the first direction in which said word lines extend, each of said plurality of data lines being connected to the sense amplifiers of a corresponding sub array, for transferring data sensed and amplified by a sense amplifier the bit line connected to which is selected;
a plurality of data buffer and multiplexer circuits formed on the semiconductor memory chip in the second direction and in parallel to said second edge of said semiconductor memory chin chip, each of said plurality of data buffer and multiplexer circuits being connected to one of said sub arrays of each of said banks; and
a plurality of input/output pads connected to said data buffer and multiplexer circuits, the input/output pads being in an arrangement in the second direction on the semiconductor memory chip and being in parallel to said second edge of said semiconductor memory, chip, the arrangement being closer to the second edge of the semiconductor memory chip than said data buffer and multiplexer circuits.
2. A dynamic type memory according to claim 1 , wherein said banks are spaced apart from each other in said second direction.
3. A dynamic type memory according to claim 1 , wherein said banks are spaced apart from each other in said first direction.
4. A dynamic type memory according to claim 1 , wherein those of said data lines which are provided for those of said sub arrays which are far from said input/output pads are over those of said sub arrays which are near to said input/output pads.
5. A dynamic type memory according to claim 2 , wherein those of said data lines which are provided for those of said sub arrays which are far from said input/output pads are over those of said sub arrays which are near to said input/output pads.
6. A dynamic type memory according to claim 3 , wherein those of said data lines which are provided for those of said sub arrays which are far from said input/output pads are over those of said sub arrays which are near to said input/output pads.
7. A dynamic type memory according to claim 1 , wherein those of said data lines which are provided for those of said sub arrays which are far from said input/output pads are arranged above portions of those of said sub arrays which are near to said input/output pads.
8. A dynamic type memory according to claim 2 , wherein those of said data lines which are provided for those of said sub arrays which are far from said input/output pads are arranged above portions of those of said sub arrays which are near to said input/output pads.
9. A dynamic type memory according to claim 3 , wherein those of said data lines which are provided for those of said sub arrays which are far from said input/output pads are arranged above portions of those of said sub arrays which are near to said input/output pads.
10. A dynamic type memory according to claim 1 , wherein a size of those of said data lines which are provided for those of said sub arrays which are far from said input/output pads is larger than that of those of the data lines which are provided for those of said sub arrays which are near to said input/output pads.
11. A dynamic type memory according to claim 2 , wherein a size of those of said data lines which are provided for those of said sub arrays which are far from said input/output pads is larger than that of those of the data lines which are provided for those of said sub arrays which are near to said input/output pads.
12. A dynamic type memory according to claim 3 , wherein a size of those of said data lines which are provided for those of said sub arrays which are far from said input/output pads is larger than that of those of the data lines which are provided for those of said sub arrays which are near to said input/output pads.
13. A semiconductor memory device, comprising:
a semiconductor chip formed on a semiconductor substrate;
a memory cell array formed on said semiconductor chip, said memory cell array comprising sub arrays organized into memory banks which are spaced apart from each other in one of a first and a second direction;
data buffer and multiplexer circuits formed on said semiconductor chip and spaced apart from each other in the second direction, each data buffer and multiplexer circuit being connected to a sub array from each memory cell bank; and
input/output pads formed on said semiconductor chip and spaced apart from each other in the second direction, each input/output pad being connected to a corresponding data buffer and multiplexer circuit,
wherein said data buffer and multiplexer circuits are arranged between said input/output pads and said sub arrays.
14. A semiconductor memory device according to claim 13 , wherein said sub arrays comprise dynamic memory cells arranged in rows and columns.
15. A semiconductor memory device according to claim 14 , further comprising:
word lines each connecting the dynamic memory cells in a row of one of said sub arrays, said word lines extending in the first direction.
16. A semiconductor memory device according to claim 15 , further comprising:
bit lines each connecting the dynamic memory cells in a column of one of said sub arrays, said bit lines extending in the second direction.
17. A semiconductor memory device according to claim 16 , further comprising:
sense amplifiers for sensing and amplifying potentials of said bit lines.
18. A semiconductor memory device according to claim 13 , further comprising:
data lines for connecting said sub arrays to said data buffer and multiplexer circuits.
19. A semiconductor memory device according to claim 18 , wherein said data buffer and multiplexer circuits are connected to the sub arrays of a first memory cell bank by first ones of said data lines having a first size and to the sub arrays of a second memory cell bank by second ones of said data lines having a second size different than the first size.
20. A semiconductor memory device according to claim 18 , wherein said data buffer and multiplexer circuits comprise switching elements connected between said data lines and said input/output pads.
21. A semiconductor memory device according to claim 13 , wherein said memory cell banks are spaced apart from each other in the first direction.
22. A semiconductor memory device according to claim 13 , wherein said memory cell banks are spaced apart from each other in the second direction.
23. A semiconductor memory device, comprising:
a semiconductor chip formed on a semiconductor substrate;
a memory cell array formed on said semiconductor chip, said memory cell array comprising sub arrays organized into memory banks which are spaced apart from each other in one of a first and a second direction, each sub array comprising memory cells arranged in rows and columns;
word lines extending in the first direction and provided for each sub array, each word line connecting memory cells in a row of the corresponding sub array;
bit lines extending in the second direction and provided for each sub array, each bit line connecting memory cells in a column of the corresponding sub array;
data buffer and multiplexer circuits formed on said semiconductor chip and spaced apart from each other in the second direction;
data lines including at least data line potions extending in the first direction and connecting said sub arrays and said data buffer and multiplexer circuits such that each data buffer and multiplexer circuit is connected to a sub array from each memory cell bank; and
input/output pads formed on said semiconductor chip and spaced apart from each other in the second direction, each input/output pad being connected to a corresponding data buffer and multiplexer circuit,
wherein said data buffer and multiplexer circuits are arranged between said input/output pads and said sub arrays.
24. A semiconductor memory device according to claim 23 , wherein said data buffer and multiplexer circuits are connected to the sub arrays of a first memory cell bank by first ones of said data lines having a first size and to the sub arrays of a second memory cell bank by second ones of said data lines having a second size different than the first size.
25. A dynamic type memory comprising:
a memory cell array formed on a semiconductor chip having a first edge and a second edge perpendicular to the first edge;
a plurality of sub arrays into which said memory cell array is divided, said plurality of sub arrays being arranged in a first direction parallel to the first edge and a second direction perpendicular to said first direction, and grouped into a plurality of banks, each of said plurality of sub arrays having a plurality of memory cells arranged in matrix;
a plurality of word lines formed on the semiconductor memory chip for each of said plurality of sub arrays and extending in the first direction, each of said plurality of word lines being connected to those of the memory cells which are in a row;
a plurality of bit lines formed on the semiconductor memory chip for each of said plurality of sub arrays and extending in the second direction, each of said plurality of bit lines being connected to those of the memory cells which are in a column;
a plurality of sense amplifiers formed on the semiconductor memory chip for each of said plurality of sub arrays and connected to said plurality of bit lines, each for sensing and amplifying a potential read out from a memory cell when a corresponding bit line is selected;
a plurality of data lines formed on the semiconductor memory chip for said plurality of sub arrays and extending in the first direction in which said word lines extend, each of said plurality of data lines being connected to the sense amplifiers of a corresponding sub array, for transferring data sensed and amplified by a sense amplifier the bit line connected to which is selected;
a plurality of multiplexer circuits formed on the semiconductor memory chip in the second direction and in parallel to the second edge of the semiconductor memory chip, each of said plurality of multiplexer circuits being connected to one of said sub arrays of each of said banks;
a plurality of data buffer circuits formed on the semiconductor memory chip in the second direction and in parallel to the second edge of the semiconductor memory chip, each of said plurality of data buffer circuits being connected to a corresponding multiplexer circuit; and
a plurality of input/output nodes connected to said data buffer circuits, said input/output nodes being in an arrangement in the second direction on the semiconductor memory chip and being in parallel to the second edge of the semiconductor memory chip, the arrangement being closer to the second edge of the semiconductor memory chip than said data buffer circuits and said multiplexer circuits.
26. A dynamic type memory according to claim 25 , wherein said banks are spaced apart from each other in the second direction.
27. A dynamic type memory according to claim 25 , wherein said banks are spaced apart from each other in the first direction.
28. A dynamic type memory according to claim 25 , wherein those of said data lines which are provided for those of said sub arrays which are far from said input/output nodes are over those of said sub arrays which are near to said input/output nodes.
29. A dynamic type memory according to claim 26 , wherein those of said data lines which are provided for those of said sub arrays which are far from said input/output nodes are over those of said sub arrays which are near to said input/output nodes.
30. A dynamic type memory according to claim 27 , wherein those of said data lines which are provided for those of said sub arrays which are far from said input/output nodes are over those of said sub arrays which are near to said input/output nodes.
31. A dynamic type memory according to claim 25 , wherein those of said data lines which are provided for those of said sub arrays which are far from said input/output nodes are arranged above portions of those of said sub arrays which are near to said input/output nodes.
32. A dynamic type memory according to claim 26 , wherein those of said data lines which are provided for those of said sub arrays which are far from said input/output nodes are arranged above portions of those of said sub arrays which are near to said input/output nodes.
33. A dynamic type memory according to claim 27 , wherein those of said data lines which are provided for those of said sub arrays which are far from said input/output nodes are arranged above portions of those of said sub arrays which are near to said input/output nodes.
34. A dynamic type memory according to claim 25 , wherein a size of those of said data lines which are provided for those of said sub arrays which are far from said input/output nodes is larger than that of those of the data lines which are provided for those of said sub arrays which are near to said input/output nodes.
35. A dynamic type memory according to claim 26 , wherein a size of those of said data lines which are provided for those of said sub arrays which are far from said input/output nodes is larger than that of those of the data lines which are provided for those of said sub arrays which are near to said input/output nodes.
36. A dynamic type memory according to claim 27 , wherein a size of those of said data lines which are provided for those of said sub arrays which are far from said input/output nodes is larger than that of those of the data lines which are provided for those of said sub arrays which are near to said input/output nodes.
37. A semiconductor memory device comprising:
a semiconductor chip formed on a semiconductor substrate;
a memory cell array formed on said semiconductor chip, said memory cell array comprising sub arrays organized into memory banks which are spaced apart from each other in one of a first and a second direction;
multiplexer circuits formed on said semiconductor chip and spaced apart from each other in the second direction, each multiplexer circuit being connected to a sub array from each memory cell bank;
data buffer circuits formed on said semiconductor chip and spaced apart from each other in the second direction, each data buffer circuit being connected to a corresponding multiplexer circuit;
input/output nodes formed on said semiconductor chip and spaced apart from each other in the second direction, each input/output node being connected to a corresponding data buffer circuit; and
wherein said data buffer circuits and said multiplexer circuits are arranged between said input/output nodes and said sub arrays.
38. A semiconductor memory device according to claim 37 , wherein said sub arrays comprise dynamic memory cells arranged in rows and columns.
39. A semiconductor memory device according to claim 38 , further comprising:
word lines each connecting the dynamic memory cells in a row of one of said sub arrays, said word lines extending in the first direction.
40. A semiconductor memory device according to claim 39 , further comprising:
bit lines each connecting the dynamic memory cells in a column of one of said sub arrays, said bit lines extending in the second direction.
41. A semiconductor memory device according to claim 40 , further comprising:
sense amplifiers for sensing and amplifying potentials of said bit lines.
42. A semiconductor memory device according to claim 37 , further comprising:
data lines for connecting said sub arrays to said multiplexer circuits.
43. A semiconductor memory device according to claim 42 , wherein said multiplexer circuits are connected to the sub arrays of a first memory cell bank by first ones of said data lines having a first size and to the sub arrays of a second memory cell bank by second ones of said data lines having a second size different than the first size.
44. A semiconductor memory device according to claim 42 , wherein said multiplexer circuits comprise switching elements connected between said data lines and said data buffer circuits.
45. A semiconductor memory device according to claim 37 , wherein said memory cell banks are spaced apart from each other in the first direction.
46. A semiconductor memory device according to claim 37 , wherein said memory cell banks are spaced apart from each other in the second direction.
47. A semiconductor memory device comprising:
a semiconductor chip formed on a semiconductor substrate;
a memory cell array formed on said semiconductor chip, said memory cell array comprising sub arrays organized into memory banks which are spaced apart from each other in one of a first and a second direction, each sub array comprising memory cells arranged in rows and columns;
word lines extending in the first direction and provided for each sub array, each word line connecting memory cells in a row of the corresponding sub array;
bit lines extending in the second direction and provided for each sub array, each bit line connecting memory cells in a column of the corresponding sub array;
multiplexer circuits formed on said semiconductor chip and spaced apart from each other in the second direction;
data buffer circuits formed on said semiconductor chip and spaced apart from each other in the second direction;
data lines including at least data line portions extending in the first direction and connecting said sub arrays and said multiplexer circuits such that each multiplexer circuit is connected to a sub array from each memory cell bank;
input/output nodes formed on said semiconductor chip and spaced apart from each other in the second direction, each input/output node being connected to a corresponding data buffer circuit; and
wherein said data buffer circuits and said multiplexer circuits are arranged between said input/output nodes and said sub arrays.
48. A semiconductor memory device according to claim 47 , wherein said multiplexer circuits are connected to the sub arrays of a first memory cell bank by first ones of said data lines having a first size and to the sub arrays of a second memory cell bank by second ones of said data lines having a second size different than the first size.
49. A dynamic type memory comprising:
a memory cell array formed on a semiconductor chip having a first edge and a second edge perpendicular to the first edge;
a plurality of sub arrays into which said memory cell array is divided, said plurality of sub arrays being arranged in a first direction parallel to the first edge and a second direction perpendicular to said first direction, and grouped into a plurality of banks, each of said plurality of sub arrays having a plurality of memory cells arranged in matrix;
a plurality of word lines formed on the semiconductor memory chip for each of said plurality of sub arrays and extending in the first direction, each of said plurality of word lines being connected to those of the memory cells which are in a row;
a plurality of bit lines formed on the semiconductor memory chip for each of said plurality of sub arrays and extending in the second direction, each of said plurality of bit lines being connected to those of the memory cells which are in a column;
a plurality of sense amplifiers formed on the semiconductor memory chip for each of said plurality of sub arrays and connected to said plurality of bit lines, each for sensing and amplifying a potential read out from a memory cell when a corresponding bit line is selected;
a plurality of data lines formed on the semiconductor memory chip for said plurality of sub arrays and extending in the first direction in which said word lines extend, each of said plurality of data lines being connected to the sense amplifiers of a corresponding sub array, for transferring data sensed and amplified by a sense amplifier the bit line connected to which is selected;
a plurality of switch circuits formed on the semiconductor memory chip in the second direction and in parallel to said second edge of said semiconductor memory chip, each of said plurality of switch circuits being connected to one of said sub arrays of each of said banks;
a plurality of data buffer circuits formed on the semiconductor memory chip in the second direction and in parallel to said second edge of said semiconductor memory chip, each of said plurality of data buffer circuits being connected to a corresponding switch circuit; and
a plurality of input/output nodes connected to said data buffer circuits, the input/output nodes being in an arrangement in the second direction on the semiconductor memory chip and being in parallel to said second edge of said semiconductor memory chip, the arrangement being closer to the second edge of the semiconductor memory chip than said data buffer circuits and said switch circuits.
50. A dynamic type memory according to claim 49 , wherein said banks are spaced apart from each other in the second direction.
51. A dynamic type memory according to claim 49 , wherein said banks are spaced apart from each other in the first direction.
52. A dynamic type memory according to claim 49 , wherein those of said data lines which are provided for those of said sub arrays which are far from said input/output nodes are over those of said sub arrays which are near to said input/output nodes.
53. A dynamic type memory according to claim 50 , wherein those of said data lines which are provided for those of said sub arrays which are far from said input/output nodes are over those of said sub arrays which are near to said input/output nodes.
54. A dynamic type memory according to claim 51 , wherein those of said data lines which are provided for those of said sub arrays which are far from said input/output nodes are over those of said sub arrays which are near to said input/output nodes.
55. A dynamic type memory according to claim 49 , wherein those of said data lines which are provided for those of said sub arrays which are far from said input/output nodes are arranged above portions of those of said sub arrays which are near to said input/output nodes.
56. A dynamic type memory according to claim 50 , wherein those of said data lines which are provided for those of said sub arrays which are far from said input/output nodes are arranged above portions of those of said sub arrays which are near to said input/output nodes.
57. A dynamic type memory according to claim 51 , wherein those of said data lines which are provided for those of said sub arrays which are far from said input/output nodes are arranged above portions of those of said sub arrays which are near to said input/output nodes.
58. A dynamic type memory according to claim 49 , wherein a size of those of said data lines which are provided for those of said sub arrays which are far from said input/output nodes is larger than that of those of the data lines which are provided for those of said sub arrays which are near to said input/output nodes.
59. A dynamic type memory according to claim 50 , wherein a size of those of said data lines which are provided for those of said sub arrays which are far from said input/output nodes is larger than that of those of the data lines which are provided for those of said sub arrays which are near to said input/output nodes.
60. A dynamic type memory according to claim 51 , wherein a size of those of said data lines which are provided for those of said sub arrays which are far from said input/output nodes is larger than that of those of the data lines which are provided for those of said sub arrays which are near to said input/output nodes.
61. A semiconductor memory device comprising:
a semiconductor chip formed on a semiconductor substrate;
a memory cell array formed on said semiconductor chip, said memory cell array comprising sub arrays organized into memory banks which are spaced apart from each other in one of a first and a second direction;
switch circuits formed on said semiconductor chip and spaced apart from each other in the second direction, each switch circuit being connected to a sub array from each memory cell bank;
data buffer circuits formed on said semiconductor chip and spaced apart from each other in the second direction, each data buffer circuit being connected to a corresponding switch circuit;
input/output nodes formed on said semiconductor chip and spaced apart from each other in the second direction, each input/output node being connected to a corresponding data buffer circuit; and
wherein said data buffer circuits and said switch circuits are arranged between said input/output nodes and said sub arrays.
62. A semiconductor memory device according to claim 61 , wherein said sub arrays comprise dynamic memory cells arranged in rows and columns.
63. A semiconductor memory device according to claim 62 , further comprising:
word lines each connecting the dynamic memory cells in a row of one of said sub arrays, said word lines extending in the first direction.
64. A semiconductor memory device according to claim 63 , further comprising:
bit lines each connecting the dynamic memory cells in a column of one of said sub arrays, said bit lines extending in the second direction.
65. A semiconductor memory device according to claim 64 , further comprising:
sense amplifiers for sensing and amplifying potentials of said bit lines.
66. A semiconductor memory device according to claim 61 , further comprising:
data lines for connecting said sub arrays to said switch circuits.
67. A semiconductor memory device according to claim 66 , wherein said switch circuits are connected to the sub arrays of a first memory cell bank by first ones of said data lines having a first size and to the sub arrays of a second memory cell bank by second ones of said data lines having a second size different than the first size.
68. A semiconductor memory device according to claim 66 , wherein said switch circuits comprise switching elements connected between said data lines and said data buffer circuits.
69. A semiconductor memory device according to claim 61 , wherein said memory cell banks are spaced apart from each other in the first direction.
70. A semiconductor memory device according to claim 61 , wherein said memory cell banks are spaced apart from each other in the second direction.
71. A semiconductor memory device comprising:
a semiconductor chip formed on a semiconductor substrate;
a memory cell array formed on said semiconductor chip, said memory cell array comprising sub arrays organized into memory banks which are spaced apart from each other in one of a first and a second direction, each sub array comprising memory cells arranged in rows and columns;
word lines extending in the first direction and provided for each sub array, each word line connecting memory cells in a row of the corresponding sub array;
bit lines extending in the second direction and provided for each sub array, each bit line connecting memory cells in a column of the corresponding sub array;
switch circuits formed on said semiconductor chip and spaced apart from each other in the second direction;
data buffer circuits formed on said semiconductor chip and spaced apart from each other in the second direction;
data lines including at least data line portions extending in the first direction and connecting said sub arrays and said switch circuits such that each switch circuit is connected to a sub array from each memory cell bank;
input/output nodes formed on said semiconductor chip and spaced apart from each other in the second direction, each input/output node being connected to a corresponding data buffer circuit; and
wherein said data buffer circuits and said switch circuits are arranged between said input/output nodes and said sub arrays.
72. A semiconductor memory device according to claim 71 , wherein said switch circuits are connected to the sub arrays of a first memory cell bank by first ones of said data lines having a first size and to the sub arrays of a second memory cell bank by second ones of said data lines having a second size different than the first size.
73. A dynamic type memory comprising:
a memory cell array formed on a semiconductor chip having a first edge and a second edge perpendicular to the first edge;
a plurality of sub arrays into which said memory cell array is divided, said plurality of sub arrays being arranged in a first direction parallel to the first edge and a second direction perpendicular to said first direction, and grouped into a plurality of banks, each of said plurality of sub arrays having a plurality of memory cells arranged in matrix;
a plurality of word lines formed on the semiconductor memory chip for each of said plurality of sub arrays and extending in the first direction, each of said plurality of word lines being connected to those of the memory cells which are in a row;
a plurality of bit lines formed on the semiconductor memory chip for each of said plurality of sub arrays and extending in the second direction, each of said plurality of bit lines being connected to those of the memory cells which are in a column;
a plurality of sense amplifiers formed on the semiconductor memory chip for each of said plurality of sub arrays and connected to said plurality of bit lines, each for sensing and amplifying a potential read out from a memory cell when a corresponding bit line is selected;
a plurality of data lines formed on the semiconductor memory chip for said plurality of sub arrays and extending in the first direction in which said word lines extend, each of said plurality of data lines being connected to the sense amplifiers of a corresponding sub array, for transferring data sensed and amplified by a sense amplifier the bit line connected to which is selected;
a plurality of multiplexer circuits formed on the semiconductor memory chip in the second direction and in parallel to said second edge of said semiconductor memory chip, each of said plurality of multiplexer circuits being connected to one of said sub arrays of each of said banks; and
a plurality of data buffer circuits formed on the semiconductor memory chip in the second direction and in parallel to said second edge of said semiconductor memory chip, each of said plurality of data buffer circuits being connected to a corresponding multiplexer circuit.
74. A dynamic type memory according to claim 73 , wherein said banks are spaced apart from each other in the second direction.
75. A dynamic type memory according to claim 73 , wherein said banks are spaced apart from each other in the first direction.
76. A dynamic type memory according to claim 73 , wherein those of said data lines which are provided for those of said sub arrays which are far from said data buffer circuits are over those of said sub arrays which are near to said data buffer circuits.
77. A dynamic type memory according to claim 74 , wherein those of said data lines which are provided for those of said sub arrays which are far from said data buffer circuits are over those of said sub arrays which are near to said data buffer circuits.
78. A dynamic type memory according to claim 75 , wherein those of said data lines which are provided for those of said sub arrays which are far from said data buffer circuits are over those of said sub arrays which are near to said data buffer circuits.
79. A dynamic type memory according to claim 73 , wherein those of said data lines which are provided for those of said sub arrays which are far from said data buffer circuits are arranged above portions of those of said sub arrays which are near to said data buffer circuits.
80. A dynamic type memory according to claim 74 , wherein those of said data lines which are provided for those of said sub arrays which are far from said data buffer circuits are arranged above portions of those of said sub arrays which are near to said data buffer circuits.
81. A dynamic type memory according to claim 75 , wherein those of said data lines which are provided for those of said sub arrays which are far from said data buffer circuits are arranged above portions of those of said sub arrays which are near to said data buffer circuits.
82. A dynamic type memory according to claim 73 , wherein a size of those of said data lines which are provided for those of said sub arrays which are far from said data buffer circuits is larger than that of those of the data lines which are provided for those of said sub arrays which are near to said data buffer circuits.
83. A dynamic type memory according to claim 74 , wherein a size of those of said data lines which are provided for those of said sub arrays which are far from said data buffer circuits is larger than that of those of the data lines which are provided for those of said sub arrays which are near to said data buffer circuits.
84. A dynamic type memory according to claim 75 , wherein a size of those of said data lines which are provided for those of said sub arrays which are far from said data buffer circuits is larger than that of those of the data lines which are provided for those of said sub arrays which are near to said data buffer circuits.
85. A semiconductor memory device comprising:
a semiconductor chip formed on a semiconductor substrate;
a memory cell array formed on said semiconductor chip, said memory cell array comprising sub arrays organized into memory banks which are spaced apart from each other in one of a first and a second direction;
multiplexer circuits formed on said semiconductor chip and spaced apart from each other in the second direction, each multiplexer circuit being connected to a sub array from each memory cell bank;
data buffer circuits formed on said semiconductor chip and spaced apart from each other in the second direction, each data buffer circuit being connected to a corresponding multiplexer circuit; and
wherein said multiplexer circuits are arranged between said data buffer circuits and said sub arrays.
86. A semiconductor memory device according to claim 85 , wherein said sub arrays comprise dynamic memory cells arranged in rows and columns.
87. A semiconductor memory device according to claim 86 , further comprising:
word lines each connecting the dynamic memory cells in a row of one of said sub arrays, said word lines extending in the first direction.
88. A semiconductor memory device according to claim 87 , further comprising:
bit lines each connecting the dynamic memory cells in a column of one of said sub arrays, said bit lines extending in the second direction.
89. A semiconductor memory device according to claim 88 , further comprising:
sense amplifiers for sensing and amplifying potentials of said bit lines.
90. A semiconductor memory device according to claim 85 , further comprising:
data lines for connecting said sub arrays to said multiplexer circuits.
91. A semiconductor memory device according to claim 90 , wherein said multiplexer circuits are connected to the sub arrays of a first memory cell bank by first ones of said data lines having a first size and to the sub arrays of a second memory cell bank by second ones of said data lines having a second size different than the first size.
92. A semiconductor memory device according to claim 90 , wherein said multiplexer circuits comprise switching elements connected between said data lines and said data buffer circuits.
93. A semiconductor memory device according to claim 85 , wherein said memory cell banks are spaced apart from each other in the first direction.
94. A semiconductor memory device according to claim 85 , wherein said memory cell banks are spaced apart from each other in the second direction.
95. A semiconductor memory device comprising:
a semiconductor chip formed on a semiconductor substrate;
a memory cell array formed on said semiconductor chip, said memory cell array comprising sub arrays organized into memory banks which are spaced apart from each other in one of a first and a second direction, each sub array comprising memory cells arranged in rows and columns;
word lines extending in the first direction and provided for each sub array, each word line connecting memory cells in a row of the corresponding sub array;
bit lines extending in the second direction and provided for each sub array, each bit line connecting memory cells in a column of the corresponding sub array;
multiplexer circuits formed on said semiconductor chip and spaced apart from each other in the second direction;
data buffer circuits formed on said semiconductor chip and spaced apart from each other in the second direction;
data lines including at least data line portions extending in the first direction and connecting said sub arrays and said multiplexer circuits such that each multiplexer circuit is connected to a sub array from each memory cell bank; and
wherein said multiplexer circuits are arranged between said data buffer circuits and said sub arrays.
96. A semiconductor memory device according to claim 95 , wherein said multiplexer circuits are connected to the sub arrays of a first memory cell bank by first ones of said data lines having a first size and to the sub arrays of a second memory cell bank by second ones of said data lines having a second size different than the first size.
97. A dynamic type memory comprising:
a memory cell array formed on a semiconductor chip having a first edge and a second edge perpendicular to the first edge;
a plurality of sub arrays into which said memory cell array is divided, said plurality of sub arrays being arranged in a first direction parallel to the first edge and a second direction perpendicular to said first direction, and grouped into a plurality of banks, each of said plurality of sub arrays having a plurality of memory cells arranged in matrix;
a plurality of word lines formed on the semiconductor memory chip for each of said plurality of sub arrays and extending in the first direction, each of said plurality of word lines being connected to those of the memory cells which are in a row;
a plurality of bit lines formed on the semiconductor memory chip for each of said plurality of sub arrays and extending in the second direction, each of said plurality of bit lines being connected to those of the memory cells which are in a column;
a plurality of sense amplifiers formed on the semiconductor memory chip for each of said plurality of sub arrays and connected to said plurality of bit lines, each for sensing and amplifying a potential read out from a memory cell when a corresponding bit line is selected;
a plurality of data lines formed on the semiconductor memory chip for said plurality of sub arrays and extending in the first direction in which said word lines extend, each of said plurality of data lines being connected to the sense amplifiers of a corresponding sub array, for transferring data sensed and amplified by a sense amplifier the bit line connected to which is selected;
a plurality of switch circuits formed on the semiconductor memory chip in the second direction and in parallel to said second edge of said semiconductor memory chip, each of said plurality of switch circuits being connected to one of said sub arrays of each of said banks; and
a plurality of data buffer circuits formed on the semiconductor memory chip in the second direction and in parallel to said second edge of said semiconductor memory chip, each of said plurality of data buffer circuits being connected to a corresponding switch circuit.
98. A dynamic type memory according to claim 97 , wherein said banks are spaced apart from each other in said second direction.
99. A dynamic type memory according to claim 97 , wherein said bands are spaced apart from each other in said first direction.
100. A dynamic type memory according to claim 97 , wherein those of said data lines which are provided for those of said sub arrays which are far from said data buffer circuits are over those of said sub arrays which are near to said data buffer circuits.
101. A dynamic type memory according to claim 98 , wherein those of said data lines which are provided for those of said sub arrays which are far from said data buffer circuits are over those of said arrays which are near to said data buffer circuits.
102. A dynamic type memory according to claim 99 , wherein those of said data lines which are provided for those of said sub arrays which are far from said data buffer circuits are over those of said sub arrays which are near to said data buffer circuits.
103. A dynamic type memory according to claim 97 , wherein those of said data lines which are provided for those of said sub arrays which are far from said data buffer circuits are arranged above portions of those of said sub arrays which are near to said data buffer circuits.
104. A dynamic type memory according to claim 98 , wherein those of said data lines which are provided for those of said sub arrays which are far from said data buffer circuits are arranged above portions of those of said sub arrays which are near to said data buffer circuits.
105. A dynamic type memory according to claim 99 , wherein those of said data lines which are provided for those of said sub arrays which are far from said data buffer circuits are arranged above portions of those of said sub arrays which are near to said data buffer circuits.
106. A dynamic type memory according to claim 97 , wherein a size of those of said data lines which are provided for those of said sub arrays which are far from said data buffer circuits is larger than that of those of the data lines which are provided for those of said sub arrays which are near to said data buffer circuits.
107. A dynamic type memory according to claim 98 , wherein a size of those of said data lines which are provided for those of said sub arrays which are far from said data buffer circuits is larger than that of those of the data lines which are provided for those of said sub arrays which are near to said data buffer circuits.
108. A dynamic type memory according to claim 99 , wherein a size of those of said data lines which are provided for those of said sub arrays which are far from said data buffer circuits is larger than that of those of the data lines which are provided for those of said sub arrays which are near to said data buffer circuits.
109. A semiconductor memory device comprising:
a semiconductor chip formed on a semiconductor substrate;
memory cell array formed on said semiconductor chip, said memory cell array comprising sub arrays organized into memory banks which are spaced apart from each other in one of a first and a second direction;
switch circuits formed on said semiconductor chip and spaced apart from each other in the second direction, each switch circuit being connected to a sub array from each memory cell bank;
data buffer circuits formed on said semiconductor chip and spaced apart from each other in the second direction, each data buffer circuit being connected to a corresponding switch circuit; and
wherein said switch circuits are arranged between said data buffer circuits and said sub arrays.
110. A semiconductor memory device according to claim 109 , wherein said sub arrays comprise dynamic memory cells arranged in rows and columns.
111. A semiconductor memory device according to claim 110 , further comprising:
word lines each connecting the dynamic memory cells in a row of one of said sub arrays, said word lines extending in the first direction.
112. A semiconductor memory device according to claim 111 , further comprising:
bit lines each connecting the dynamic memory cells in a column of one of said sub arrays, said bit lines extending in the second direction.
113. A semiconductor memory device according to claim 112 , further comprising:
sense amplifiers for sensing and amplifying potentials of said bit lines.
114. A semiconductor memory device according to claim 109 , further comprising:
data lines for connecting said sub arrays to said switch circuits.
115. A semiconductor memory device according to claim 114 , wherein said switch circuits are connected to the sub arrays of a first memory cell bank by first ones of said data lines having a first size and to the sub arrays of a second memory cell bank by second ones of said data lines having a second size different than the first size.
116. A semiconductor memory device according to claim 114 , wherein said switch circuits comprise switching elements connected between said data lines and said data buffer circuits.
117. A semiconductor memory device according to claim 109 , wherein said memory cell banks are spaced apart from each other in the first direction.
118. A semiconductor memory device according to claim 109 , wherein said memory cell banks are spaced apart from each other in the second direction.
119. A semiconductor memory device comprising:
a semiconductor chip formed on a semiconductor substrate;
a memory cell array formed on said semiconductor chip, said memory cell array comprising sub arrays organized into memory banks which are spaced apart from each other in one of a first and a second direction, each sub array comprising memory cells arranged in rows and columns;
word lines extending in the first direction and provided for each sub array, each word line connecting memory cells in a row of the corresponding sub array;
bit lines extending in the second direction and provided for each sub array, each bit line connecting memory cells in a column of the corresponding sub array;
switch circuits formed on said semiconductor chip and spaced apart from each other in the second direction;
data buffer circuits formed on said semiconductor chip and spaced apart from each other in the second direction;
data lines including at least data line portions extending in the first direction and connecting said sub arrays and said switch circuits such that each switch circuit is connected to a sub array from each memory cell bank; and
wherein said switch circuits are arranged between said data buffer circuits and said sub arrays.
120. A semiconductor memory device according to claim 119 , wherein said switch circuits are connected to the sub arrays of a first memory cell bank by first ones of said data lines having a first size and to the sub arrays of a second memory cell bank by second ones of said data lines having a second size different than the first size.Cited by (0)
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