Inventor

KARVE GAURI

US70 patents

⚠️ This page may combine multiple inventors who share the name “KARVE GAURI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KARVE GAURI

IBM

Cutting fins and gates in CMOS devices

Preventing strained fin relaxation

FinFET device with channel strain

Preventing strained fin relaxation by sealing fin ends

Channel protection during fin fabrication

FinFET device with channel strain

Semiconductor device and method of forming the semiconductor device

Semiconductor device and method of forming the semiconductor device

Semiconductor device and method of forming the semiconductor device

Semiconductor device and method of forming the semiconductor device

Sublithography gate cut physical unclonable function

Super long channel device within VFET architecture

Preventing strained fin relaxation

FinFET device having a high germanium content fin structure and method of making same

Margin for fin cut using self-aligned triple patterning

Stress retention in fins of fin field-effect transistors

Strained finFET device fabrication

Nanosheet substrate to source/drain isolation

Magnetoresistive random access memory thin film transistor unit cell

Substrate isolated VTFET devices

Separate N and P fin etching for reduced CMOS device leakage

Integration of input/output device in vertical field-effect transistor technology

Sub-fin removal for SOI like isolation with uniform active fin height

Super long channel device within VFET architecture

Semiconductor device and method of forming the semiconductor device

Semiconductor device and method of forming the semiconductor device

Bilayer hardmask for direct print lithography

Forming MOSFET structures with work function modification

Secure fingerprinting of a trusted photomask

Structure and method for equal substrate to channel height between N and P fin-FETs

Physical unclonable function

Elevator analytics facilitating passenger destination prediction and resource optimization

Transistor gate having tapered segments positioned above the fin channel

Integration of input/output device in vertical field-effect transistor technology

Nanosheet transistor barrier for electrically isolating the substrate from the source or drain regions

Utilizing multilayer gate spacer to reduce erosion of semiconductor Fin during spacer patterning

Integration of input/output device in vertical field-effect transistor technology

Super long channel device within VFET architecture

Sub-fin removal for SOI like isolation with uniform active fin height

Margin for fin cut using self-aligned triple patterning

Utilizing multilayer gate spacer to reduce erosion of semiconductor fin during spacer patterning

Stress retention in fins of fin field-effect transistors

Stress retention in fins of fin field-effect transistors

Under-channel gate transistors

Forming MOSFET structures with work function modification

Structure and process to tuck fin tips self-aligned to gates

Structure and process to tuck fin tips self-aligned to gates

Channel replacement and bimodal doping scheme for bulk finFet threshold voltage modulation with reduced performance penalty

ST MICROELECTRONICS INC

FinFET device having a high germanium content fin structure and method of making same

TESSERA LLC

Structure and process to tuck fin tips self-aligned to gates