Structure and process to tuck fin tips self-aligned to gates

Abstract

A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

What is claimed is: 
     
       1. A semiconductor structure comprising:
 a semiconductor fin portion having an end wall and extending upwards from a substrate; 
 a gate structure straddling a portion of said semiconductor fin portion; 
 a first set of gate spacers located on opposing sidewall surfaces of said gate structure; and 
 a second set of gate spacers located on outer sidewalls of said first gate spacers, wherein one gate spacer of said second set of gate spacers has an inner sidewall surface having an upper portion directly contacting said outer sidewall of one of said gate spacers of said first set of gate spacers and a lower portion directly contacting and covering an entirety of a sidewall of said end wall of said semiconductor fin portion, wherein:
 another gate spacer of said second set of gate spacers straddles over a topmost surface of a portion of said semiconductor fin portion. 
 
 
     
     
       2. The semiconductor structure of  claim 1 , wherein said gate structure is a functional gate structure. 
     
     
       3. The semiconductor structure of  claim 2 , wherein each gate spacer of said first set of gate spacers is only located on a said topmost surface of said semiconductor fin portion, and wherein one gate spacer of said first set of gate spacers has an outer edge that is vertically aligned to said sidewall of said end wall of said semiconductor fin portion. 
     
     
       4. The semiconductor structure of  claim 3 , wherein another gate spacer of said second set of gate spacers straddles over said topmost surface of said semiconductor fin portion. 
     
     
       5. The semiconductor structure of  claim 2 , wherein each gate spacer of said first set of gate spacers straddles over said semiconductor fin portion. 
     
     
       6. The semiconductor structure of  claim 5 , wherein another gate spacer of said second set of gate spacers straddles another portion of said semiconductor fin portion. 
     
     
       7. The semiconductor structure of  claim 1 , wherein said substrate is an insulator layer. 
     
     
       8. The semiconductor structure of  claim 1 , wherein said first set of gate spacers comprises a same dielectric material as said second set of gate spacers. 
     
     
       9. The semiconductor structure of  claim 1 , wherein said first set of gate spacers comprise a different dielectric material than said second set of gate spacers. 
     
     
       10. The semiconductor structure of  claim 1 , wherein at least one gate spacer of said first set of gate spacers or said second set of gate spacers is composed of a SiBCN or SiOCN material. 
     
     
       11. The semiconductor structure of  claim 1 , wherein one gate spacer of said first set of gate spacers has an outer surface that is vertically aligned with said sidewall surface of said end wall of said semiconductor fin portion. 
     
     
       12. The semiconductor structure of  claim 1 , wherein a bottommost surface of each gate spacer of said second set of gate spacers is coplanar with a bottommost surface of said semiconductor fin portion. 
     
     
       13. A semiconductor structure comprising:
 a semiconductor fin portion having an end wall and extending upwards from a substrate;   a gate structure straddling a portion of said semiconductor fin portion;   a first set of gate spacers located on opposing sidewall surfaces of said gate structure; and   a second set of gate spacers located on outer sidewalls of said first gate spacers, wherein one gate spacer of said second set of gate spacers has an inner sidewall surface having an upper portion directly contacting said outer sidewall of one of said gate spacers of said first set of gate spacers, wherein among the second set of gate spacers, only said one gate spacer of said second set of gate spacers has a lower portion directly contacting and covering an entirety of a sidewall of said end wall of said semiconductor fin portion, and wherein another gate spacer of said second set of gate spacers straddles another portion of said semiconductor fin portion.    
     
     
       14. The semiconductor structure of  claim 13 , wherein said gate structure is a functional gate structure.  
     
     
       15. The semiconductor structure of  claim 14 , wherein one gate spacer of said first set of gate spacers has an outer surface that is vertically aligned to said sidewall of said end wall of said semiconductor fin portion.  
     
     
       16. The semiconductor structure of  claim 14 , wherein each gate spacer of said first set of gate spacers straddles over said semiconductor fin portion.  
     
     
       17. The semiconductor structure of  claim 13 , wherein said substrate is a semiconductor-on-insulator (SOI) substrate.  
     
     
       18. The semiconductor structure of  claim 13 , wherein said first set of gate spacers comprises a same dielectric material as said second set of gate spacers.  
     
     
       19. The semiconductor structure of  claim 13 , wherein said first set of gate spacers comprises a different dielectric material than said second set of gate spacers.  
     
     
       20. The semiconductor structure of  claim 13 , wherein at least one gate spacer of said first set of gate spacers or said second set of gate spacers comprises a SiBCN material.  
     
     
       21. The semiconductor structure of  claim 13 , wherein at least one gate spacer of said first set of gate spacers or said second set of gate spacers comprises a SiOCN material.  
     
     
       22. The semiconductor structure of  claim 13 , wherein one gate spacer of said first set of gate spacers has an outer surface that is vertically aligned with said sidewall surface of said end wall of said semiconductor fin portion.  
     
     
       23. The semiconductor structure of  claim 13 , wherein said one gate spacer of said second set of gate spacers is coplanar with a bottommost surface of said semiconductor fin portion.  
     
     
       24. The semiconductor structure of  claim 13 , wherein at least one gate spacer of said first set of gate spacers has a maximum thickness of about 10 nm.