Inventor · disambiguated record
Fee Li Lie
Also filed as: LIE FEE LI
176 granted patents·14 pending applications·886 citations·filing 2014–2024
99Inventor score
Top patents by PatentIndex Score
190 records- 0199US10553522B1Semiconductor microcoolerIBM·Filed 2018·Granted Feb 4, 2020·20 cites·6 claims
- 0299US9620590B1Nanosheet channel-to-source and drain isolationIBM·Filed 2016·Granted Apr 11, 2017·105 cites·13 claims
- 0399US9608065B1Air gap spacer for metal gatesIBM·Filed 2016·Granted Mar 28, 2017·141 cites·20 claims
- 0498US11043581B2Nanosheet channel-to-source and drain isolationTESSERA INC·Filed 2020·Granted Jun 22, 2021·4 cites·11 claims
- 0598US9842931B1Self-aligned shallow trench isolation and doping for vertical fin transistorsIBM·Filed 2016·Granted Dec 12, 2017·33 cites·15 claims
- 0698US9805935B2Bottom source/drain silicidation for vertical field-effect transistor (FET)IBM·Filed 2015·Granted Oct 31, 2017·27 cites·18 claims
- 0798US9799765B1Formation of a bottom source-drain for vertical field-effect transistorsIBM·Filed 2016·Granted Oct 24, 2017·28 cites·14 claims
- 0898US9748380B1Vertical transistor including a bottom source/drain region, a gate structure, and an air gap formed between the bottom source/drain region and the gate structureIBM·Filed 2016·Granted Aug 29, 2017·32 cites·11 claims
- 0998US9472506B2Registration mark formation during sidewall image transfer processIBM·Filed 2015·Granted Oct 18, 2016·26 cites·7 claims
- 1098US9450095B1Single spacer for complementary metal oxide semiconductor process flowIBM·Filed 2016·Granted Sep 20, 2016·24 cites·16 claims
- 1198US9362179B1Method to form dual channel semiconductor material finsIBM·Filed 2015·Granted Jun 7, 2016·41 cites·14 claims
- 1297US10304744B1Inverse tone direct print EUV lithography enabled by selective material depositionIBM·Filed 2018·Granted May 28, 2019·23 cites·14 claims
- 1397US9853127B1Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer processIBM·Filed 2016·Granted Dec 26, 2017·18 cites·5 claims
- 1497US9754798B1Hybridization fin reveal for uniform fin reveal depth across different fin pitchesIBM·Filed 2016·Granted Sep 5, 2017·17 cites·16 claims
- 1596US11699591B2Two-color self-aligned double patterning (SADP) to yield static random access memory (SRAM) and dense logicTESSERA LLC·Filed 2021·Granted Jul 11, 2023·2 cites·20 claims
- 1696US11652161B2Nanosheet channel-to-source and drain isolationTESSERA LLC·Filed 2021·Granted May 16, 2023·2 cites·21 claims
- 1796US10074730B2Forming stacked nanowire semiconductor deviceIBM·Filed 2016·Granted Sep 11, 2018·11 cites·17 claims
- 1896US9536750B1Method for fin formation with a self-aligned directed self-assembly process and cut-last schemeIBM·Filed 2015·Granted Jan 3, 2017·14 cites·8 claims
- 1995US10014391B2Vertical transport field effect transistor with precise gate length definitionIBM·Filed 2016·Granted Jul 3, 2018·10 cites·10 claims
- 2095US10002962B2Vertical FET structureIBM·Filed 2016·Granted Jun 19, 2018·11 cites·18 claims
- 2195US9917196B1Semiconductor device and method of forming the semiconductor deviceIBM·Filed 2016·Granted Mar 13, 2018·8 cites·8 claims
- 2295US9842739B2Method and structure for enabling high aspect ratio sacrificial gatesIBM·Filed 2016·Granted Dec 12, 2017·8 cites·16 claims
- 2395US9755071B1Merged gate for vertical transistorsIBM·Filed 2016·Granted Sep 5, 2017·10 cites·15 claims
- 2495US9728622B1Dummy gate formation using spacer pull down hardmaskIBM·Filed 2016·Granted Aug 8, 2017·11 cites·18 claims
- 2595US9589958B1Pitch scalable active area patterning structure and process for multi-channel finFET technologiesIBM·Filed 2016·Granted Mar 7, 2017·12 cites·16 claims
- 2695US9318574B2Method and structure for enabling high aspect ratio sacrificial gatesIBM·Filed 2014·Granted Apr 19, 2016·16 cites·15 claims
- 2795US9305845B2Self-aligned quadruple patterning processIBM·Filed 2014·Granted Apr 5, 2016·17 cites·19 claims
- 2894US11079337B1Secure wafer inspection and identificationIBM·Filed 2020·Granted Aug 3, 2021·3 cites·20 claims
- 2994US10615269B2Nanosheet channel-to-source and drain isolationIBM·Filed 2018·Granted Apr 7, 2020·5 cites·12 claims
- 3094US10553516B1Semiconductor microcoolerIBM·Filed 2018·Granted Feb 4, 2020·10 cites·6 claims
- 3194US10381437B2Semiconductor device and method of forming the semiconductor deviceIBM·Filed 2017·Granted Aug 13, 2019·6 cites·11 claims
- 3294US10249730B1Controlling gate profile by inter-layer dielectric (ILD) nanolaminatesIBM·Filed 2017·Granted Apr 2, 2019·11 cites·15 claims
- 3394US10249738B2Nanosheet channel-to-source and drain isolationIBM·Filed 2016·Granted Apr 2, 2019·6 cites·9 claims
- 3493US11239316B2Semiconductor device and method of forming the semiconductor deviceIBM·Filed 2019·Granted Feb 1, 2022·4 cites·20 claims
- 3592US11127815B2Semiconductor device and method of forming the semiconductor deviceIBM·Filed 2019·Granted Sep 21, 2021·4 cites·20 claims
- 3692US10211316B2Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer processIBM·Filed 2017·Granted Feb 19, 2019·6 cites·14 claims
- 3792US10043801B2Air gap spacer for metal gatesIBM·Filed 2017·Granted Aug 7, 2018·5 cites·20 claims
- 3892US9881937B2Preventing strained fin relaxationIBM·Filed 2017·Granted Jan 30, 2018·6 cites·10 claims
- 3992US9331148B1FinFET device with channel strainIBM·Filed 2015·Granted May 3, 2016·6 cites·9 claims
- 4091US9640640B1FinFET device with channel strainIBM·Filed 2016·Granted May 2, 2017·5 cites·9 claims
- 4191US9595613B1Forming semiconductor fins with self-aligned patterningIBM·Filed 2016·Granted Mar 14, 2017·5 cites·20 claims
- 4291US9496371B1Channel protection during fin fabricationIBM·Filed 2015·Granted Nov 15, 2016·7 cites·20 claims
- 4391US9425196B1Multiple threshold voltage FinFETsIBM·Filed 2015·Granted Aug 23, 2016·7 cites·18 claims
- 4491US2025142856A1Nanosheet channel-to-source and drain isolationADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2024·Application pending·0 cites
- 4590US9786666B2Method to form dual channel semiconductor material finsIBM·Filed 2016·Granted Oct 10, 2017·5 cites·13 claims
- 4690US9659779B2Method and structure for enabling high aspect ratio sacrificial gatesIBM·Filed 2014·Granted May 23, 2017·7 cites·16 claims
- 4789US11520768B2Vertical transistor and method of forming the vertical transistorIBM·Filed 2020·Granted Dec 6, 2022·2 cites·20 claims
- 4889US10833190B2Super long channel device within VFET architectureIBM·Filed 2019·Granted Nov 10, 2020·4 cites·15 claims
- 4989US10734523B2Nanosheet substrate to source/drain isolationIBM·Filed 2018·Granted Aug 4, 2020·6 cites·20 claims
- 5089US9576979B2Preventing strained fin relaxation by sealing fin endsIBM·Filed 2015·Granted Feb 21, 2017·5 cites·9 claims
Showing the top 50 of 190 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →