Inventor

SIEG STUART A

US60 patents

⚠️ This page may combine multiple inventors who share the name “SIEG STUART A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SIEG STUART A

IBM

Inverse tone direct print EUV lithography enabled by selective material deposition

Cutting fins and gates in CMOS devices

Registration mark formation during sidewall image transfer process

Self-aligned quadruple patterning process

finFET isolation by selective cyclic etch

Self-aligned double patterning formed fincut

Alternating hardmasks for tight-pitch line formation

Direct gate patterning for vertical transport field effect transistor

Pitch scalable active area patterning structure and process for multi-channel finFET technologies

Front side wafer ID processing

Alternating hardmasks for tight-pitch line formation

Patterning assist feature to mitigate reactive ion etch microloading effect

Vertical transport static random-access memory cells with transistors of active regions arranged in linear rows

Alternating hardmasks for tight-pitch line formation

Gate cut on a vertical field effect transistor with a defined-width inorganic mask

Pitch scalable active area patterning structure and process for multi-channel fin FET technologies

Margin for fin cut using self-aligned triple patterning

Gate cut on a vertical field effect transistor with a defined-width inorganic mask

Stress retention in fins of fin field-effect transistors

Gate cutting for a vertical transistor device

Strained finFET device fabrication

Alternating hardmasks for tight-pitch line formation

Registration mark formation during sidewall image transfer process

Vertical transistor with variable gate length

Fin cut profile using fin base liner

Vertical transport devices with greater density through modified well shapes

Tunable hardmask for overlayer metrology contrast

Fin field effect transistor devices with self-aligned gates

Vertical transistors having multiple gate thicknesses for optimizing performance and device density

Vertical transistors having multiple gate thicknesses for optimizing performance and device density

Controlling fin hardmask cut profile using a sacrificial epitaxial structure

Approach to prevent collapse of high aspect ratio Fin structures for vertical transport Fin field effect transistor devices

Tunable hardmask for overlayer metrology contrast

Margin for fin cut using self-aligned triple patterning

Stress retention in fins of fin field-effect transistors

Stress retention in fins of fin field-effect transistors

Structure and process to tuck fin tips self-aligned to gates

Structure and process to tuck fin tips self-aligned to gates

Strained finFET device fabrication

Strained FinFET device fabrication

Structure and process to tuck fin tips self-aligned to gates

Self-aligned quadruple patterning process

Strained finFET device fabrication

Strained finFET device fabrication

TESSERA LLC

Alternating hardmasks for tight-pitch line formation

Structure and process to tuck fin tips self-aligned to gates

TESSERA INC

Alternating hardmasks for tight-pitch line formation

Alternating hardmasks for tight-pitch line formation

GLOBALFOUNDRIES INC

Methods to control fin tip placement

ADEIA SEMICONDUCTOR SOLUTIONS LLC

Alternating hardmasks for tight-pitch line formation