Inventor

OYAMATSU HISATO

JP34 patents

⚠️ This page may combine multiple inventors who share the name “OYAMATSU HISATO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OYAMATSU HISATO

TOSHIBA KK

Semiconductor chip which combines bulk and SOI regions and separates same with plural isolation regions

Semiconductor device including a plurality of kinds of MOS transistors having different gate widths and method of manufacturing the same

Method for manufacturing a semiconductor device having a limited pocket region

Semiconductor chip which combines bulk and SOI regions and separates same with plural isolation regions

Semiconductor chip having multiple functional blocks integrated in a single chip and method for fabricating the same

Semiconductor device having one of patterned SOI and SON structure

Semiconductor device using partial SOI substrate and manufacturing method thereof

Semiconductor device having patterned SOI structure and method for fabricating the same

Semiconductor device and method for manufacturing same

N-channel MOSFET having STI structure and method for manufacturing the same

Semiconductor apparatus and manufacturing method therefor

Manufacturing method of MOSFET having salicide structure

Method for manufacturing MOSFET having an LDD structure

Semiconductor device having structure suitable for CMP process

Semiconductor device comprising multiple layers with trenches formed on a semiconductor substrate

Semiconductor device having patterned SOI structure and method for fabricating the same

Semiconductor device having patterned SOI structure and method for fabricating the same

Method for manufacturing multilayer wiring structure semiconductor device

Semiconductor device

Method of fabricating semiconductor device

Semiconductor device having channel with cooling fluid and manufacturing method thereof

Semiconductor device using partial SOI substrate and manufacturing method thereof

Semiconductor device using partial SOI substrate and manufacturing method thereof

Semiconductor device with an improved gate electrode pattern

Semiconductor device with high speed operation and high integration

Semiconductor wafer, method of manufacturing the same and semiconductor device

Magnetic memory device

Semiconductor device having metal silicide layer on source/drain region and gate electrode and method of manufacturing the same

Cooling semiconductor device and manufacturing method thereof

Semiconductor device substrate including a single-crystalline layer and method of manufacturing semiconductor device substrate

Semiconductor device having metal silicide layer on source/drain region and gate electrode and method of manufacturing the same

Semiconductor device with an improved gate electrode pattern and a method of manufacturing the same

FUJII OSAMU

Manufacturing system for semiconductor device capable of controlling variation in electrical property of element in wafer surface and method for manufacturing the semiconductor device

TOKYO SHIBAURA ELECTRIC CO

Method of manufacturing a semiconductor device including a plurality of kinds of MOS transistors having different gate widths