Inventor

CHOU JIH-WEN

TW61 patents

⚠️ This page may combine multiple inventors who share the name “CHOU JIH-WEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHOU JIH-WEN

UNITED MICROELECTRONICS CORP

Method of fabricating field effect transistor

Method for fabricating a metal-oxide semiconductor transistor

Low triggering voltage SOI silicon-control-rectifier (SCR) structure

Air-gap spacer of a metal-oxide-semiconductor device

Method of fabricating the high-density diode-based read-only memory device

Method of fabricating high density semiconductor read-only memory device

Method for manufacturing shallow trench isolation

Diode-based semiconductor read-only memory device and method of fabricating the same

Method of fabricating a MOS transistor with local channel ion implantation regions

Method for implementing metal oxide semiconductor field effect transistor

Method for producing PMOS devices

Method for fabricating metal oxide semiconductor

Method for fabricating a metal-oxide semiconductor device

Method of fabricating metal oxide semiconductor

Method for manufacturing thick gate oxide device

Metal-oxide semiconductor field effect transistor device fabrication process

Method of fabricating an air-gap spacer of a metal-oxide-semiconductor device

Method of forming lightly doped drains in metalic oxide semiconductor components

Method of fabricating dual voltage MOS transistors

Method of forming a MOS transistor

Method for forming MOSFET

Super halo implant combined with offset spacer process

Method for manufacturing semiconductor device capable of preventing gate-to-drain capacitance and eliminating birds beak formation

Method for manufacturing dual gate oxide layer

Method for a pre-amorphization

Semiconductor device having varied dopant density regions

Method of suppressing junction capacitance of source/drain regions

Method for fabricating a metal-oxide semiconductor transistor

Method of manufacturing shallow trench isolation

Fabrication of buried channel devices with shallow junction depth

Method for reducing or avoiding the formation of a silicon recess in SDE junction regions

Structure of a spacer

Method of fabricating salicide

Method of fabricating flat-cell mask read-only memory (ROM) devices

SEG combined with tilt side implant process

Method for forming a metal-oxide-semiconductor transistor

Method for forming gate

Method for fabricating high-density semiconductor read-only memory device

EMEMORY TECHNOLOGY INC

Method for programming, erasing and reading a flash memory cell

Method of forming an embedded memory including forming three silicon or polysilicon layers

Method for operating a NAND-array memory module composed of P-type memory cells

PROMOS TECHNOLOGIES INC

Method for fabricating memory cell

Fabrication method of metal oxide semiconductor transistor

Semicondutor device and manufacturing method thereof

UNITED MICROELECTRICS CORP

Fabrication of buried channel devices with shallow junction depth

Method of fabricating metal-oxide semiconductor (MOS) transistors with reduced level of degradation caused by hot carriers

UNITED SEMICONDUCTOR CORP

Method of reducing fringe capacitance

UNITED MICOELECTRONICS CORP

Method for forming a transistor with selective epitaxial growth film

UNITED MIROELECTRONICS CORP

Method of forming a metallic oxide semiconductor

UNITED MICROELTRONICS CORP

High-density semiconductor read-only memory device