Semicondutor device and manufacturing method thereof

Abstract

A semiconductor device is provided. The semiconductor device has a gate structure, a source region, a drain region, and a pair of dielectric barrier layers. The gate structure is formed on a substrate. The source region and the drain region are formed in the substrate next to the gate structure, and a channel region is formed between the source region and the drain region underneath the gate structure. The pair of dielectric barrier layers is respectively formed in the substrate underneath the gate structure between the source region and the drain region. The dielectric barrier layers are used for reducing the drain induced barrier lowering effect in a nanometer scale device.

1. A method for forming a semiconductor device comprising:
 providing a substrate; 
 forming a gate structure on the substrate; 
 removing a portion of the substrate, using the gate structure as a mask, to form an opening with a depth in the substrate beside both sides of the gate structure; 
 forming a first dielectric barrier layer on the substrate exposed by the opening; 
 forming a second dielectric barrier layer on sidewalls of the gate structure and the substrate underneath the gate structure; 
 removing the first dielectric barrier layer not covered by the second dielectric barrier layer; 
 forming a first semiconductive layer in the opening with a thickness, wherein the thickness is less than the depth; 
 removing a portion of the second dielectric barrier layer higher than a surface of the first semiconductive layer; 
 forming a second semiconductive layer in the opening; and 
 forming a source region and a drain region in the second semiconductive layer and the first semiconductive layer beside both sides of the gate structure. 
 
   
   
     2. The method of  claim 1 , wherein after the step of removing the portion of the second dielectric barrier layer higher than the surface of the first semiconductive layer, the method further comprising removing a portion of the first dielectric barrier layer higher than a surface of the first semiconductive layer. 
   
   
     3. The method of  claim 1 , wherein a material of the first dielectric barrier layer comprises silicon oxide. 
   
   
     4. The method of  claim 1 , wherein the first dielectric barrier layer on the substrate exposed by the opening is formed by a thermal oxidation process or a chemical vapor deposition process. 
   
   
     5. The method of  claim 1 , wherein the step of forming the second dielectric barrier layer on sidewalls of the gate structure and the substrate underneath the gate structure comprises:
 forming a dielectric material layer on the substrate; and 
 performing an anisotropic etching process to remove a portion of the dielectric material layer. 
 
   
   
     6. The method of  claim 1 , wherein a material of the second dielectric barrier layer comprises silicon nitride. 
   
   
     7. The method of  claim 1 , wherein a material of the first semiconductive layer and the second semiconductive layer comprises epitaxial silicon. 
   
   
     8. The method of  claim 6 , wherein a method of forming the first semiconductive layer and the second semiconductive layer comprises selective epitaxial growing.