Inventor
MALAVIYA SHASHI D
US26 patents
⚠️ This page may combine multiple inventors who share the name “MALAVIYA SHASHI D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
23 patentsUS4508579AApr 2, 1985
Lateral device structures using self-aligned fabrication techniques
IBM273 citations99
US4704368ANov 3, 1987
Method of making trench-incorporated monolithic semiconductor capacitor and high density dynamic memory cells including the capacitor
IBM72 citations96
US4396999AAug 2, 1983
Tunneling transistor memory cell
IBM63 citations96
US4739252AApr 19, 1988
Current attenuator useful in a very low leakage current measuring device
IBM88 citations95
US5243140ASep 7, 1993
Direct distribution repair and engineering change system
IBM33 citations92
US4771328ASep 13, 1988
Semiconductor device and process
IBM52 citations92
US4764799AAug 16, 1988
Stud-defined integrated circuit structure
IBM31 citations92
US4758528AJul 19, 1988
Self-aligned metal process for integrated circuit metallization
IBM38 citations92
US4661832AApr 28, 1987
Total dielectric isolation for integrated circuits
IBM29 citations92
US4648173AMar 10, 1987
Fabrication of stud-defined integrated circuit structure
IBM35 citations92
US4502913AMar 5, 1985
Total dielectric isolation for integrated circuits
IBM50 citations92
US4400865AAug 30, 1983
Self-aligned metal process for integrated circuit metallization
IBM46 citations92
US4131861ADec 26, 1978
Variable frequency oscillator system including two matched oscillators controlled by a phase locked loop
IBM44 citations92
US4743565AMay 10, 1988
Lateral device structures using self-aligned fabrication techniques
IBM18 citations74
US4608589AAug 26, 1986
Self-aligned metal structure for integrated circuits
IBM11 citations74
US4196363AApr 1, 1980
Open collector bit driver/sense amplifier
IBM10 citations74
US4058808ANov 15, 1977
High performance analog to digital converter for integrated circuits
IBM13 citations74
US4746815AMay 24, 1988
Electronic EC for minimizing EC pads
IBM8 citations72
US4584763AApr 29, 1986
One mask technique for substrate contacting in integrated circuits involving deep dielectric isolation
IBM5 citations63
US4431305AFeb 14, 1984
High density DC stable memory cell
IBM6 citations63
US4319148AMar 9, 1982
High speed 3-way exclusive OR logic circuit
IBM5 citations63
US4743781AMay 10, 1988
Dotting circuit with inhibit function
IBM1 citations51
US4409673AOct 11, 1983
Single isolation cell for DC stable memory
IBM0 citations42