Inventor

XIANG QI

US208 patents

Patents

50 patents

US6800910B2Oct 5, 2004

FinFET device incorporating strained silicon in the channel region

ADVANCED MICRO DEVICES INC295 citations99

US6703648B1Mar 9, 2004

Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication

ADVANCED MICRO DEVICES INC200 citations99

US6682973B1Jan 27, 2004

Formation of well-controlled thin SiO, SiN, SiON layer for multilayer high-K dielectric applications

ADVANCED MICRO DEVICES INC595 citations99

US6657276B1Dec 2, 2003

Shallow trench isolation (STI) region with high-K liner and method of formation

ADVANCED MICRO DEVICES INC198 citations99

US6657223B1Dec 2, 2003

Strained silicon MOSFET having silicon source/drain regions and method for its fabrication

ADVANCED MICRO DEVICES INC173 citations99

US6600170B1Jul 29, 2003

Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors

ADVANCED MICRO DEVICES INC154 citations99

US6255169B1Jul 3, 2001

Process for fabricating a high-endurance non-volatile memory device

ADVANCED MICRO DEVICES INC268 citations99

US6093594AJul 25, 2000

CMOS optimization method utilizing sacrificial sidewall spacer

ADVANCED MICRO DEVICES INC264 citations99

US7138302B2Nov 21, 2006

Method of fabricating an integrated circuit channel region

ADVANCED MICRO DEVICES INC70 citations98

US7078299B2Jul 18, 2006

Formation of finFET using a sidewall epitaxial layer

ADVANCED MICRO DEVICES INC118 citations98

US7071051B1Jul 4, 2006

Method for forming a thin, high quality buffer layer in a field effect transistor and related structure

ADVANCED MICRO DEVICES INC550 citations98

US6902991B2Jun 7, 2005

Semiconductor device having a thick strained silicon layer and method of its formation

ADVANCED MICRO DEVICES INC76 citations98

US6855982B1Feb 15, 2005

Self aligned double gate transistor having a strained channel region and process therefor

ADVANCED MICRO DEVICES INC103 citations98

US6811448B1Nov 2, 2004

Pre-cleaning for silicidation in an SMOS process

ADVANCED MICRO DEVICES INC123 citations98

US6797602B1Sep 28, 2004

Method of manufacturing a semiconductor device with supersaturated source/drain extensions and metal silicide contacts

ADVANCED MICRO DEVICES INC113 citations98

US6787864B2Sep 7, 2004

Mosfets incorporating nickel germanosilicided gate and methods for their formation

ADVANCED MICRO DEVICES INC126 citations98

US6707106B1Mar 16, 2004

Semiconductor device with tensile strain silicon introduced by compressive material in a buried oxide layer

ADVANCED MICRO DEVICES INC91 citations98

US6630720B1Oct 7, 2003

Asymmetric semiconductor device having dual work function gate and method of fabrication

ADVANCED MICRO DEVICES INC75 citations98

US6586808B1Jul 1, 2003

Semiconductor device having multi-work function gate electrode and multi-segment gate dielectric

ADVANCED MICRO DEVICES INC86 citations98

US6562718B1May 13, 2003

Process for forming fully silicided gates

ADVANCED MICRO DEVICES INC107 citations98

US6555879B1Apr 29, 2003

SOI device with metal source/drain and method of fabrication

ADVANCED MICRO DEVICES INC135 citations98

US6479866B1Nov 12, 2002

SOI device with self-aligned selective damage implant, and method

ADVANCED MICRO DEVICES INC120 citations98

US6475874B2Nov 5, 2002

Damascene NiSi metal gate high-k transistor

ADVANCED MICRO DEVICES INC137 citations98

US6410938B1Jun 25, 2002

Semiconductor-on-insulator device with nitrided buried oxide and method of fabricating

ADVANCED MICRO DEVICES INC114 citations98

US6300203B1Oct 9, 2001

Electrolytic deposition of dielectric precursor materials for use in in-laid gate MOS transistors

ADVANCED MICRO DEVICES INC101 citations98

US6211044B1Apr 3, 2001

Process for fabricating a semiconductor device component using a selective silicidation reaction

ADVANCED MICRO DEVICES INC242 citations98

US6187657B1Feb 13, 2001

Dual material gate MOSFET technique

ADVANCED MICRO DEVICES INC120 citations98

US6159782ADec 12, 2000

Fabrication of field effect transistors having dual gates with gate dielectrics of high dielectric constant

ADVANCED MICRO DEVICES INC126 citations98

US6087231AJul 11, 2000

Fabrication of dual gates of field transistors with prevention of reaction between the gate electrode and the gate dielectric with a high dielectric constant

ADVANCED MICRO DEVICES INC102 citations98

US6955969B2Oct 18, 2005

Method of growing as a channel region to reduce source/drain junction capacitance

ADVANCED MICRO DEVICES INC89 citations97

US6943087B1Sep 13, 2005

Semiconductor on insulator MOSFET having strained silicon channel

ADVANCED MICRO DEVICES INC59 citations96

US6929992B1Aug 16, 2005

Strained silicon MOSFETs having NMOS gates with work functions for compensating NMOS threshold voltage shift

ADVANCED MICRO DEVICES INC78 citations96

US6787423B1Sep 7, 2004

Strained-silicon semiconductor device

ADVANCED MICRO DEVICES INC69 citations96

US6656749B1Dec 2, 2003

In-situ monitoring during laser thermal annealing

ADVANCED MICRO DEVICES INC57 citations96

US6555439B1Apr 29, 2003

Partial recrystallization of source/drain region before laser thermal annealing

ADVANCED MICRO DEVICES INC53 citations96

US6524929B1Feb 25, 2003

Method for shallow trench isolation using passivation material for trench bottom liner

ADVANCED MICRO DEVICES INC51 citations96

US6514809B1Feb 4, 2003

SOI field effect transistors with body contacts formed by selective etch and fill

ADVANCED MICRO DEVICES INC54 citations96

US6465309B1Oct 15, 2002

Silicide gate transistors

ADVANCED MICRO DEVICES INC57 citations96

US6437404B1Aug 20, 2002

Semiconductor-on-insulator transistor with recessed source and drain

ADVANCED MICRO DEVICES INC64 citations96

US6200863B1Mar 13, 2001

Process for fabricating a semiconductor device having assymetric source-drain extension regions

ADVANCED MICRO DEVICES INC64 citations96

US6180469B1Jan 30, 2001

Low resistance salicide technology with reduced silicon consumption

ADVANCED MICRO DEVICES INC69 citations96

US5937315AAug 10, 1999

Self-aligned silicide gate technology for advanced submicron MOS devices

ADVANCED MICRO DEVICES INC51 citations96

US5960322ASep 28, 1999

Suppression of boron segregation for shallow source and drain junctions in semiconductors

ADVANCED MICRO DEVICES INC64 citations94

US7217608B1May 15, 2007

CMOS with strained silicon channel NMOS and silicon germanium channel PMOS

ADVANCED MICRO DEVICES INC26 citations93

US7170084B1Jan 30, 2007

Strained silicon MOSFET having improved source/drain extension dopant diffusion resistance and method for its fabrication

ADVANCED MICRO DEVICES INC21 citations93

US7033893B1Apr 25, 2006

CMOS devices with balanced drive currents based on SiGe

ADVANCED MICRO DEVICES INC21 citations93

US7015078B1Mar 21, 2006

Silicon on insulator substrate having improved thermal conductivity and method of its formation

ADVANCED MICRO DEVICES INC28 citations93

Showing the top 50 of 208 patents by PatentIndex Score.

XIANG QI

Patents

FinFET device incorporating strained silicon in the channel region

Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication

Formation of well-controlled thin SiO, SiN, SiON layer for multilayer high-K dielectric applications

Shallow trench isolation (STI) region with high-K liner and method of formation

Strained silicon MOSFET having silicon source/drain regions and method for its fabrication

CMOS with strained silicon channel NMOS and silicon germanium channel PMOS

MOSFETs with differing gate dielectrics and method of formation

MOSFET device having high-K dielectric layer

Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors

Process for fabricating a high-endurance non-volatile memory device

CMOS optimization method utilizing sacrificial sidewall spacer

Method of fabricating an integrated circuit channel region

Formation of finFET using a sidewall epitaxial layer

Method for forming a thin, high quality buffer layer in a field effect transistor and related structure

Semiconductor device having a thick strained silicon layer and method of its formation

Self aligned double gate transistor having a strained channel region and process therefor

Pre-cleaning for silicidation in an SMOS process

Method of manufacturing a semiconductor device with supersaturated source/drain extensions and metal silicide contacts

Mosfets incorporating nickel germanosilicided gate and methods for their formation

Semiconductor device with tensile strain silicon introduced by compressive material in a buried oxide layer

Asymmetric semiconductor device having dual work function gate and method of fabrication

Semiconductor device having multi-work function gate electrode and multi-segment gate dielectric

Process for forming fully silicided gates

SOI device with metal source/drain and method of fabrication

SOI device with self-aligned selective damage implant, and method

Damascene NiSi metal gate high-k transistor

Semiconductor-on-insulator device with nitrided buried oxide and method of fabricating

Electrolytic deposition of dielectric precursor materials for use in in-laid gate MOS transistors

Process for fabricating a semiconductor device component using a selective silicidation reaction

Dual material gate MOSFET technique

Fabrication of field effect transistors having dual gates with gate dielectrics of high dielectric constant

Fabrication of dual gates of field transistors with prevention of reaction between the gate electrode and the gate dielectric with a high dielectric constant

Method of growing as a channel region to reduce source/drain junction capacitance

Semiconductor on insulator MOSFET having strained silicon channel

Strained silicon MOSFETs having NMOS gates with work functions for compensating NMOS threshold voltage shift

Strained-silicon semiconductor device

In-situ monitoring during laser thermal annealing

Partial recrystallization of source/drain region before laser thermal annealing

Method for shallow trench isolation using passivation material for trench bottom liner

SOI field effect transistors with body contacts formed by selective etch and fill

Silicide gate transistors

Semiconductor-on-insulator transistor with recessed source and drain

Process for fabricating a semiconductor device having assymetric source-drain extension regions

Low resistance salicide technology with reduced silicon consumption

Self-aligned silicide gate technology for advanced submicron MOS devices

Suppression of boron segregation for shallow source and drain junctions in semiconductors

CMOS with strained silicon channel NMOS and silicon germanium channel PMOS

Strained silicon MOSFET having improved source/drain extension dopant diffusion resistance and method for its fabrication

CMOS devices with balanced drive currents based on SiGe

Silicon on insulator substrate having improved thermal conductivity and method of its formation