Inventor

PENDHARKAR SAMEER P

US58 patents

⚠️ This page may combine multiple inventors who share the name “PENDHARKAR SAMEER P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PENDHARKAR SAMEER P

TEXAS INSTRUMENTS INC

Reduced surface field device having an extended field plate and method for forming the same

Reduced surface field device having an extended field plate and method for forming the same

Integrated circuit which minimizes parasitic action in a switching transistor pair

Efficient protection structure for reverse pin-to-pin electrostatic discharge

Method of manufacturing and structure of semiconductor device with floating ring structure

Drain extend MOS transistor with improved breakdown robustness

Method of manufacturing and structure of semiconductor device with floating ring structure

ESD robust bipolar transistor with high variable trigger and sustaining voltages

Diluted drift layer with variable stripe widths for power transistors

LDMOS transistor double diffused region formation process

System and method for making a LDMOS device with electrostatic discharge protection

System and method for making a LDMOS device with electrostatic discharge protection

Deep trench with self-aligned sinker

Isolation trench with rounded corners for BiCMOS process

Segmented power MOSFET of safe operation

Hybrid active-field gap extended drain MOS transistor

Integrated high-side driver for P-N bimodal power device

Implant profiling with resist

Implant profiling with resist

Transistor having double isolation with one floating isolation

Poly sandwich for deep trench fill

High voltage multiple channel LDMOS

Bladed silicon-on-insulator semiconductor devices and method of making

Hybrid active-field gap extended drain MOS transistor

Drain extended MOS transistor with improved breakdown robustness

Distributed power MOSFET

Integrated circuit device with a vertical JFET

Integrated trench capacitor

Poly sandwich for deep trench fill

Method of using electrical test structure for semiconductor trench depth monitor

Method for manufacturing a semiconductor device having an alignment feature formed using an N-type dopant and a wet oxidation process

Low leakage power transistor and method of forming

Bladed silicon-on-insulator semiconductor devices and method of making

Integrated high-side driver for P-N bimodal power device

Structures to avoid floating resurf layer in high voltage lateral devices

Integrated trench capacitor

P-N bimodal transistors

Structures to avoid floating RESURF layer in high voltage lateral devices

High breakdown n-type buried layer

Hybrid active-field gap extended drain MOS transistor

P-N bimodal conduction resurf LDMOS

High breakdown N-type buried layer

PENDHARKAR SAMEER P

Buried floating layer structure for improved breakdown

Hybrid active-field gap extended drain MOS transistor

Low resistance LDMOS with reduced gate charge

High voltage diode with reduced substrate injection

High voltage diode with reduced substrate injection

High voltage SCRMOS in BiCMOS process technologies

Isolation trench with rounded corners for BiCMOS process

BURGESS BYRON NEVILLE

Low cost high voltage power FET and fabrication