LDMOS transistor double diffused region formation process

Abstract

Exemplary embodiments provide manufacturing methods for forming a doped region in a semiconductor. Specifically, the doped region can be formed by multiple ion implantation processes using a patterned photoresist (PR) layer as a mask. The patterned PR layer can be formed using a hard-bakeless photolithography process by removing a hard-bake step to improve the profile of the patterned PR layer. The multiple ion implantation processes can be performed in a sequence of, implanting a first dopant species using a high energy; implanting the first dopant species using a reduced energy and an increased implant angle (e.g., about 9° or higher); and implanting a second dopant species using a reduced energy. In various embodiments, the doped region can be used as a double diffused region for LDMOS transistors.

1. A method for forming a double diffused region of a laterally diffused metal oxide semiconductor (LDMOS) transistor, comprising:
 forming a patterned photoresist layer over a semiconductor substrate without hard baking; 
 forming a first doped region by implanting a first boron-containing species into a region of the semiconductor substrate through the non-hard baked patterned photoresist layer at an implant energy of 300 KeV or greater in a high energy tool; 
 following forming the first doped region, forming a second doped region by implanting a second boron-containing species into the semiconductor substrate region through the non-hard baked patterned photoresist layer at an implant energy of 200 KeV or less in a reduced energy tool; wherein the second doped region is shallower than the first doped region and wherein the energy used to form the first doped region functions to cure the non-hard baked patterned photoresist layer prior to forming the second doped region to reduce outgassing during implanting the second boron-containing species; 
 forming a third doped region by implanting an arsenic-containing species into the semiconductor region through each opening of the patterned photoresist layer in a reduced energy tool; and 
 thermally annealing the semiconductor. 
 
   
   
     2. The method of  claim 1 , wherein the second doped region is formed by implanting the second boron-containing species at an implant angle of about 9° or higher. 
   
   
     3. The method of  claim 1 , wherein the semiconductor region is a deep n-well region in an epitaxial layer of the semiconductor. 
   
   
     4. The method of  claim 1 , wherein the first doped region is formed using an energy of 300 KeV to about 600 KeV with a dose of about 1×10 12  cm −2  to about 1×10 14  cm −2  in an MeV tool. 
   
   
     5. The method of  claim 4 , wherein the second boron-containing species are the same; and the second doped region is formed using an energy of about 20 KeV to 200 KeV with a dose of about 1×10 13  cm −2  to about 5×10 14  cm −2  in a mid-current tool. 
   
   
     6. The method of  claim 5 , wherein the third doped region is formed following forming the second doped region and using an energy of about 120 KeV to about 200 KeV with a dose of about 1×10 13  cm −2  to about 2×10 14  cm −2  in the mid-current tool. 
   
   
     7. The method of  claim 1 , wherein the thermal annealing occurs at a temperature of about 800° C. or more. 
   
   
     8. A method for forming a laterally diffused metal oxide semiconductor (LDMOS) transistor, comprising:
 forming a deep n-well region in an epitaxial layer on a semiconductor substrate; 
 forming a patterned photoresist layer over the deep n-well region, wherein the patterned photoresist layer is formed without hard baking; 
 implanting a boron species into the deep n-well region through the non-hard baked patterned photoresist layer in a first implantation using an energy of 300 KeV or greater; 
 following the first implantation, implanting the boron species into the deep n-well region through the non-hard baked patterned photoresist layer in a second implantation using an energy of 200 KeV or less and an implant angle of 12° or more; and 
 forming a gate dielectric layer on the deep n-well region; 
 whereby the energy of the first implantation functions to cure the non-hard baked patterned photoresist layer to reduce outgassing during the second implantation; and the implant angle of the second implantation functions to compensate an implant tail from the first implantation. 
 
   
   
     9. The method of  claim 8 , further comprising implanting an arsenic species into the deep n-well region through the patterned photoresist layer in a third implantation using an energy of 200 KeV or less. 
   
   
     10. The method of  claim 8 , further comprising forming isolation structures in the deep n-well region; wherein the isolation structures are STI (shallow trench isolation) structures or LOCOS (local oxidation of silicon) structures. 
   
   
     11. The method of  claim 8 , further comprising forming isolation structures in the deep n-well region prior to the first implantation of the boron species. 
   
   
     12. The method of  claim 8 , further comprising a thermal annealing process at a temperature of about 800° C. to about 1200° C. performed following the first and second implantations. 
   
   
     13. The method of  claim 12 , wherein the thermal annealing process is performed as part of a thermal oxidation process used to form isolation structures in the deep n-well.