Inventor
FRANKLIN ANDREW J
US19 patents
⚠️ This page may combine multiple inventors who share the name “FRANKLIN ANDREW J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
NAT SEMICONDUCTOR CORP
16 patentsUS6711051B1Mar 23, 2004
Static RAM architecture with bit line partitioning
NAT SEMICONDUCTOR CORP82 citations97
US7239558B1Jul 3, 2007
Method of hot electron injection programming of a non-volatile memory (NVM) cell array in a single cycle
NAT SEMICONDUCTOR CORP28 citations92
US7167392B1Jan 23, 2007
Non-volatile memory cell with improved programming technique
NAT SEMICONDUCTOR CORP35 citations92
US6992927B1Jan 31, 2006
Nonvolatile memory cell
NAT SEMICONDUCTOR CORP38 citations92
US6563730B1May 13, 2003
Low power static RAM architecture
NAT SEMICONDUCTOR CORP35 citations92
US7558969B1Jul 7, 2009
Anti-pirate circuit for protection against commercial integrated circuit pirates
NAT SEMICONDUCTOR CORP21 citations90
US7656698B1Feb 2, 2010
Non-volatile memory cell with improved programming technique with decoupling pass gates and equalize transistors
NAT SEMICONDUCTOR CORP14 citations84
US7042763B1May 9, 2006
Programming method for nonvolatile memory cell
NAT SEMICONDUCTOR CORP18 citations84
US7164606B1Jan 16, 2007
Reverse fowler-nordheim tunneling programming for non-volatile memory cell
NAT SEMICONDUCTOR CORP17 citations83
US6618282B1Sep 9, 2003
High density ROM architecture with inversion of programming
NAT SEMICONDUCTOR CORP14 citations80
US7020027B1Mar 28, 2006
Programming method for nonvolatile memory cell
NAT SEMICONDUCTOR CORP10 citations74
US8363469B1Jan 29, 2013
All-NMOS 4-transistor non-volatile memory cell
NAT SEMICONDUCTOR CORP6 citations72
US7126866B1Oct 24, 2006
Low power ROM architecture
NAT SEMICONDUCTOR CORP10 citations72
US6642587B1Nov 4, 2003
High density ROM architecture
NAT SEMICONDUCTOR CORP10 citations72
US7061792B1Jun 13, 2006
Low AC power SRAM architecture
NAT SEMICONDUCTOR CORP2 citations62
US7286383B1Oct 23, 2007
Bit line sharing and word line load reduction for low AC power SRAM architecture
NAT SEMICONDUCTOR CORP6 citations58