Inventor

BULUCEA CONSTANTIN

US71 patents

⚠️ This page may combine multiple inventors who share the name “BULUCEA CONSTANTIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BULUCEA CONSTANTIN

NAT SEMICONDUCTOR CORP

Field-effect transistor for alleviating short-channel effects

Field-effect transistor having multi-part channel

Fabrication of multiple field-effect transistor structure having local threshold-adjust doping

Fabrication of complementary field-effect transistors each having multi-part channel

Fabrication of semiconductor structure having N-channel channel-junction field-effect transistor

Fabrication of semiconductor structure in which complementary field-effect transistors each have hypoabrupt body dopant distribution below at least one source/drain zone

Configuration and fabrication of semiconductor structure having n-channel channel-junction field-effect transistor

Use of mask shadowing and angled implantation in fabricating asymmetrical field-effect transistors

Field-effect transistor having local threshold-adjust doping

Design and fabrication of semiconductor structure having complementary channel-junction insulated-gate field-effect transistors whose gate electrodes have work functions close to mid-gap semiconductor value

Semiconductor structure in which like-polarity insulated-gate field-effect transistors have multiple vertical body dopant concentration maxima and different halo pocket characteristics

Fabrication of field-effect transistor for alleviating short-channel effects

Fabrication of bipolar transistors using selective doping to improve performance characteristics

P-channel field-effect transistor with reduced junction capacitance

CMOS latchup suppression by localized minority carrier lifetime reduction

Fabrication of field-effect transistor having hypoabrupt body dopant distribution below source/drain zone

Semiconductor architecture having field-effect transistors especially suitable for analog applications

Gate-enhanced junction varactor

Gate-enhanced junction varactor with gradual capacitance variation

Field-effect transistor having multi-part channel

Method of manufacturing insulated gate semiconductor device to improve ruggedness

Insulated gate semiconductor device typically having subsurface-peaked portion of body region for improved ruggedness

Array spreading resistance probe (ASRP) method for profile extraction from semiconductor chips of cellular construction

Fabrication of field-effect transistor with reduced junction capacitance and threshold voltage of magnitude that decreases with increasing channel length

Fabrication of like-polarity insulated-gate field-effect transistors having multiple vertical body dopant concentration maxima and different halo pocket characteristics

Fabrication of p-channel field-effect transistor for reducing junction capacitance

Fabrication of bipolar transistors with improved output current-voltage characteristics

Bipolar transistors using isolated selective doping to improve performance characteristics

CMOS latchup suppression by localized minority carrier lifetime reduction

Integration of trench power transistors into a 1.5 μm BCD process

Semiconductor structure utilizing empty and filled wells

Fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications

Gate-enhanced junction varactor

Configuration and fabrication of semiconductor structure using empty and filled wells

Semiconductor architecture having field-effect transistors especially suitable for analog applications

Insulated-gate field-effect transistor with hypoabrupt step change in body dopant concentration below source/drain zone

Fabrication of complementary field-effect transistors with vertical body-material dopant profiles tailored to alleviate punchthrough and reduce current leakage

BULUCEA CONSTANTIN

Fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications

Structure and fabrication of insulated-gate field-effect transistor with hypoabrupt change in body dopant concentration below source/drain zone

Configuration and fabrication of semiconductor structure using empty and filled wells

Structure and fabrication of field-effect transistor using empty well in combination with source/drain extensions or/and halo pocket

Semiconductor architecture having field-effect transistors especially suitable for analog applications

SILICONIX INC

DMOS power transistor with reduced number of contacts using integrated body-source connections

Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry

Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry

DMOS power transistors with reduced number of contacts using integrated body-source connections

Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry

YANG JENG-JIUN

Fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portion along source/drain zone

PARKER D COURTNEY

Fabrication of asymmetric field-effect transistors using L-shaped spacers

IDEAL POWER INC

Semiconductor device with bi-directional double-base trench power switches