P
US7701005B1ExpiredUtilityPatentIndex 96

Semiconductor structure in which like-polarity insulated-gate field-effect transistors have multiple vertical body dopant concentration maxima and different halo pocket characteristics

Assignee: NAT SEMICONDUCTOR CORPPriority: Mar 31, 2000Filed: Oct 15, 2007Granted: Apr 20, 2010
Est. expiryMar 31, 2020(expired)· nominal 20-yr term from priority
Inventors:BULUCEA CONSTANTINWANG FU-CHENGCHAPARALA PRASAD
H10D 84/0167H10D 84/038H10D 84/017H10D 62/314H10D 62/371
96
PatentIndex Score
33
Cited by
29
References
22
Claims

Abstract

Each of a pair of differently configured like-polarity insulated-gate field-effect transistors ( 40 or 42 and 240 or 242 ) in a semiconductor structure has a channel zone of semiconductor body material, a gate dielectric layer overlying the channel zone, and a gate electrode overlying the gate dielectric layer. For each transistor, the net dopant concentration of the body material reaches multiple local subsurface maxima below a channel surface depletion region and below largely all gate-electrode material overlying the channel zone. The transistors have source/drain zones ( 60 or 80 ) of opposite conductivity type to, and halo pocket portions of the same conductivity type as, the body material. One pocket portion ( 100/102 or 104 ) extends along both source/drain zones of one of the transistors. Another pocket portion ( 244 or 246 ) extends largely along only one of the source/drain zones of the other transistor so that it is asymmetrical.

Claims

exact text as granted — not AI-modified
1. A structure comprising a pair of like-polarity first and second field-effect transistors (“FETs”) provided along an upper surface of a semiconductor body having body material of a first conductivity type, each FET comprising:
 a channel zone of the body material; 
 a pair of source/drain zones situated in the semiconductor body along its upper surface, laterally separated by the channel zone, and being of a second conductivity type opposite to the first conductivity type so as to form respective pn junctions with the body material; 
 a gate dielectric layer overlying the channel zone; and 
 a gate electrode overlying the gate dielectric layer above the channel zone such that (a) the body material has a net dopant concentration which reaches a plurality of local subsurface maxima below a channel surface depletion region extending along the body's upper surface into the channel zone and (b) each of the local subsurface maxima in the body material's net dopant concentration is located below largely all material of the gate electrode overlying the channel zone, wherein (i) a pocket portion of the body material more heavily doped than laterally adjacent material of the body material extends along each of the source/drain zones of the first FET and (ii) a pocket portion of the body material more heavily doped than laterally adjacent material of the body material extends largely along only one of the source/drain zones of the second FET and into its channel zone such that the channel zone of the second FET is asymmetrical. 
 
   
   
     2. A structure as in  claim 1  wherein at least one of the local subsurface maxima in the body material's net dopant concentration occurring below largely all material of the gate electrode of each FET overlying its channel zone underlies at least part of each of that FET's source/drain zones. 
   
   
     3. A structure as in  claim 1  wherein at least one of the local subsurface maxima in the body material's net dopant concentration occurring below largely all material of the gate electrode of each FET overlying its channel zone underlies substantially all of each of that FET's source/drain zones. 
   
   
     4. A structure as in  claim 1  wherein each of at least two of the local subsurface maxima in the body material's net dopant concentration occurring below largely all material of the gate electrode of each FET overlying its channel zone underlies at least part of each of that FET's source/drain zones. 
   
   
     5. A structure as in  claim 1  wherein each of at least two of the local subsurface maxima in the body material's net dopant concentration occurring below largely all material of the gate electrode of each FET overlying its channel zone underlies substantially all of each of that FET's source/drain zones. 
   
   
     6. A structure as in  claim 1  wherein the pocket portion of the first FET comprises two pocket segments apart from each other, each pocket segment extending along a different one of the first FET's source/drain zones. 
   
   
     7. A structure as in  claim 6  wherein the pocket segments of the first FET are situated generally symmetrically along its source/drain zones. 
   
   
     8. A structure as in  claim 1  wherein the pocket portion of the first FET extends continuously between its source/drain zones. 
   
   
     9. A structure as in  claim 8  wherein the pocket portion of the first FET is situated generally symmetrically along its source/drain zones. 
   
   
     10. A structure as in  claim 1  wherein each source/drain zone comprises a main source/drain portion and a more lightly doped source/drain extension laterally continuous with the main source/drain portion, the channel zone of each FET being terminated by that FET's source/drain extensions along the body's upper surface. 
   
   
     11. A structure comprising a pair of like-polarity first and second field-effect transistors (“FETs”) provided along an upper surface of a semiconductor body having body material of a first conductivity type, each FET comprising:
 a channel zone of the body material; 
 a pair of source/drain zones situated in the semiconductor body along its upper surface, laterally separated by the channel zone, and being of a second conductivity type opposite to the first conductivity type so as to form respective pn junctions with the body material; 
 a gate dielectric layer overlying the channel zone; and 
 a gate electrode overlying the gate dielectric layer above the channel zone such that (a) the body material has a net dopant concentration which reaches a plurality of local subsurface maxima below a channel surface depletion region extending along the body's upper surface into the channel zone and (b) each of the local subsurface maxima in the body material's net dopant concentration is located below largely all material of the gate electrode overlying the channel zone, wherein (i) the channel zone of the first FET has a net dopant concentration which substantially reaches a plurality of local surface maxima in moving longitudinally from one of the first FET's source/drain zones along the body's upper surface to the other of the first FET's source/drain zones and (ii) the channel zone of the second FET has a net dopant concentration which substantially reaches only a single local surface maximum in moving longitudinally from one of the second FET's source/drain zones along the body's upper surface to the other of the second FET's source/drain zones, the local surface maximum in the net dopant concentration in the channel zone of the second FET occurring materially closer to one of its source/drain zones than to the other of its source/drain zones such that its channel zone is asymmetrical. 
 
   
   
     12. A structure as in  claim 11  wherein the plurality of local surface maxima of the net dopant concentration in the channel zone of the first FET is two. 
   
   
     13. A structure as in  claim 12  wherein the two local surface maxima of the net dopant concentration in the channel zone of the first FET occur at locations largely symmetrical relative to its source/drain zones. 
   
   
     14. A structure as in  claim 11  wherein each source/drain zone comprises a main source/drain portion and a more lightly doped source/drain extension laterally continuous with the main source/drain portion, the channel zone of each FET being terminated by that FET's source/drain extensions along the body's upper surface. 
   
   
     15. A structure as in  claim 1  wherein one of the subsurface maxima in the body material's net dopant concentration occurring below largely all material of the gate electrode of each FET overlying its channel zone occurs at a depth sufficiently below the body's upper surface as to materially inhibit punchthrough of the source/drain regions of that FET. 
   
   
     16. A structure as in  claim 1  wherein one of the subsurface maxima in the body material's net dopant concentration occurring below largely all material of the gate electrode of each FET overlying its channel zone occurs at a depth of more than 0.1 μm below the body's upper surface. 
   
   
     17. A structure as in  claim 1  wherein the plurality of local subsurface maxima of the body material's net dopant concentration occurring below largely all material of the gate electrode of the first FET overlying its channel zone is at least three. 
   
   
     18. A structure as in  claim 17  wherein each subsurface maxima in the net dopant concentration of the body material occurs at a depth of more than 0.1 μm below the body's upper surface. 
   
   
     19. A structure as in  claim 11  wherein one of the subsurface maxima in the net dopant concentration occurring below largely all material of the gate electrode of each FET overlying its channel zone  occurs at a depth sufficiently below the body's upper surface as to materially inhibit punchthrough of the source/drain regions of that FET. 
   
   
     20. A structure as in  claim 11  wherein each subsurface maxima in the body material's net dopant concentration occurring below largely all material of the gate electrode of each FET overlying its channel zone occurs at a depth of more than 0.1 μm below the body's upper surface. 
   
   
     21. A structure as in  claim 11  wherein the plurality of local subsurface maxima of the body material's net dopant concentration occurring below largely all material of the gate electrode of the first FET overlying its channel zone is at least three. 
   
   
     22. A structure as in  claim 21  wherein each subsurface maxima in the body material's net dopant concentration occurring below largely all material of the gate electrode of each FET overlying its channel zone occurs at a depth of more than 0.1 μm below the body's upper surface.

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