Inventor

CHAPARALA PRASAD

US20 patents

⚠️ This page may combine multiple inventors who share the name “CHAPARALA PRASAD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHAPARALA PRASAD

NAT SEMICONDUCTOR CORP

Field-effect transistor for alleviating short-channel effects

Semiconductor structure in which like-polarity insulated-gate field-effect transistors have multiple vertical body dopant concentration maxima and different halo pocket characteristics

Fabrication of field-effect transistor for alleviating short-channel effects

P-channel field-effect transistor with reduced junction capacitance

Fabrication of field-effect transistor with reduced junction capacitance and threshold voltage of magnitude that decreases with increasing channel length

Fabrication of like-polarity insulated-gate field-effect transistors having multiple vertical body dopant concentration maxima and different halo pocket characteristics

Direct implantation of fluorine into the channel region of a PMOS device

Fabrication of p-channel field-effect transistor for reducing junction capacitance

Configuration and fabrication of semiconductor structure using empty and filled wells

Method of monitoring process misalignment to reduce asymmetric device operation and improve the electrical and hot carrier performance of LDMOS transistor arrays

Method and structure for testing metal-insulator-metal capacitor structures under high temperature at wafer level

Fabrication of complementary field-effect transistors with vertical body-material dopant profiles tailored to alleviate punchthrough and reduce current leakage

Method of programming an antifuse

Structure and fabrication of field-effect transistor for alleviating short-channel effects

Method for testing metal-insulator-metal capacitor structures under high temperature at wafer level

MOS transistor and method of forming the MOS transistor with a SiON etch stop layer that protects the transistor from PID and hot carrier degradation

BULUCEA CONSTANTIN

Configuration and fabrication of semiconductor structure using empty and filled wells

Fabrication of field-effect transistor with vertical body-material dopant profile tailored to alleviate punchthrough and reduce current leakage

CHAPARALA PRASAD

Structure and fabrication of field-effect transistor having nitrided gate dielectric layer with tailored vertical nitrogen concentration profile

Structure and fabrication of field-effect transistor having nitrided gate dielectric layer with tailored vertical nitrogen concentration profile