Inventor

HUANG RU

CN67 patents

⚠️ This page may combine multiple inventors who share the name “HUANG RU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HUANG RU

HUANG RU

Method for testing density and location of gate dielectric layer trap of semiconductor device

High voltage-resistant lateral double-diffused transistor based on nanowire device

Fabrication method for surrounding gate silicon nanowire transistor with air as spacers

Ge-based NMOS device and method for fabricating the same

Strained channel field effect transistor and the method for fabricating the same

Heat dissipation structure of SOI field effect transistor

MOS transistor having combined-source structure with low power consumption and method for fabricating the same

Combined-source MOS transistor with comb-shaped gate, and method for manufacturing the same

Method for fabricating complementary tunneling field effect transistor based on standard CMOS IC process

Method for fabricating surrounding-gate silicon nanowire transistor with air sidewalls

Field effect transistor with a vertical channel and fabrication method thereof

Method for fabricating a tunneling field-effect transistor

Electrostatic discharge protection device and method for fabricating the same

Method for predicting reliable lifetime of SOI mosfet device

Method for fabricating silicon nanowire field effect transistor based on wet etching

Tunneling current amplification transistor

Interface treatment method for germanium-based device

Fabrication method of vertical silicon nanowire field effect transistor

Method for introducing channel stress and field effect transistor fabricated by the same

Multilevel resistive memory having large storage capacity

Method for testing trap density of gate dielectric layer in semiconductor device having no substrate contact

UNIV BEIJING

Integration method for a vertical nanowire transistor

Method for fabricating ultra-fine nanowire

Resistive memory and method for fabricating the same

Radiation-hardened-by-design (RHBD) multi-gate device

Highly reliable nonvolatile memory and manufacturing method thereof

Method for fabricating FinFET with separated double gates on bulk silicon

Self-adaptive composite tunneling field effect transistor and method for fabricating the same

Method of adjusting a threshold voltage of a multi-gate structure device

Method for implementing adaptive stochastic spiking neuron based on ferroelectric field effect transistor

Short-gate tunneling field effect transistor having non-uniformly doped vertical channel and fabrication method thereof

Resistive random access memory with high uniformity and low power consumption and method for fabricating the same

Strip-shaped gate tunneling field effect transistor with double-diffusion and a preparation method thereof

Strip-shaped gate-modulated tunneling field effect transistor and a preparation method thereof

Compute-in-memory circuit based on charge redistribution, and control method thereof

Preparation method of a germanium-based schottky junction

Method for processing gate dielectric layer deposited on germanium-based or group III-V compound-based substrate

Resistive memory and method for fabricating the same

CAI YIMAO

Resistive memory cell

Resistive memory with small electrode and method for fabricating the same

I-shape floating gate for flash memory device and fabricating the same

Resistive-switching memory and fabrication method thereof

HANGZHOU WEIMING XINKE TECH CO LTD

CMOS-MEMS humidity sensor

Logic circuit design method

HANG ZHOU NANO CORE CHIP ELECTRONIC TECH CO LTD

Capacitance-to-digital conversion circuit, a capacitance-to-digital conversion method and an electronic chip

Power-aware method, power-aware system and converter

LI MING

Method for fabricating a finFET in a large scale integrated circuit

CADENCE DESIGN SYSTEMS INC

Method of bias temperature instability calculation and prediction for MOSFET and FinFET

YE LE

Directional coupler integrated by CMOS process

AN XIA

Semiconductor device and method for fabricating the same