Inventor

RAMARAJU RAVINDRARAJ

US120 patents

⚠️ This page may combine multiple inventors who share the name “RAMARAJU RAVINDRARAJ”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RAMARAJU RAVINDRARAJ

FREESCALE SEMICONDUCTOR INC

Data latch with structural hold

Memory redundancy to replace addresses with multiple errors

Method for powering an electronic device and circuit

Storage circuit with efficient sleep mode and method

Bit line precharge in embedded memory

Storage device having low power mode and methods thereof

Integrated circuit having a low power mode and method therefor

Dual-port static random access memory having improved cell stability and write margin

Integrated circuit storage element having low power data retention and method therefor

Method and apparatus for controlling current demand in an integrated circuit

Temperature sensor circuit

Adaptive error correction codes (ECCs) for electronic memories

Capacitively coupled input buffer

Master-slave flip-flop with reduced setup time

Word line fault detection

Static random access memory (SRAM) having bit cells accessible by separate read and write paths

Circuit for a low power mode

Circuit and method for latch bypass

Data latch with minimal setup time and launch delay

Content addressable memory with search line test circuitry

Memory device having concurrent write and read cycles and method thereof

Contention-free keeper circuit and a method for contention elimination

Method and apparatus for low voltage write in a static random access memory

Memory reliability using error-correcting code

Non-volatile static random access memory (NVSRAM) having a shared port

Error repair location cache

Mismatch-compensated sense amplifier for highly scaled technology

Error correction with extended CAM

RAMARAJU RAVINDRARAJ

Multi-core system on chip

Reconfigurable flip-flop

Memory with word line access control

In-line register file bitcell

Integrated circuit having low power mode voltage regulator

Hierarchical error correction for large memories

Sequential digital circuitry with test scan

Hierarchical error correction

Data type dependent memory scrubbing

Flip-flop having shared feedback and method of operation

Error detection within a memory

Memory voltage regulator with leakage current voltage control

Data processor having multiple low power modes

R&D 3 LLC

Method and circuit device incorporating time-to-transition signal node sensing

Memory device having variable impedance memory cells and time-to-transition sensing of data stored therein

Memory device having variable impedance memory cells and time-to-transition sensing of data stored therein

PELLEY PERRY H

Charge pump system and method of operation

Non-volatile memory using bi-directional resistive elements and capacitive elements

Multi-port register file with multiplexed data

BAKER JR FRANK K

Non-volatile memory using bi-directional resistive elements

HOEKSTRA GEORGE P

Dynamic logic circuit

NGUYEN HUY B

Memory with low voltage mode operation