Inventor
PAWLOWSKI STEPHEN
US12 patents
Patents
12 patentsUS6263397B1Jul 17, 2001
Mechanism for delivering interrupt messages
INTEL CORP51 citations93
US6151663ANov 21, 2000
Cluster controller for memory and data cache in a multiple cluster processing system
INTEL CORP42 citations92
US5961621AOct 5, 1999
Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system
INTEL CORP32 citations92
US5848279ADec 8, 1998
Mechanism for delivering interrupt messages
INTEL CORP30 citations92
US5829052AOct 27, 1998
Method and apparatus for managing memory accesses in a multiple multiprocessor cluster system
INTEL CORP17 citations92
US5513331AApr 30, 1996
Method and apparatus for automatically configuring system memory address space of a computer system having a memory subsystem with indeterministic number of memory units of indeterministic sizes during system reset
INTEL CORP32 citations92
US5301299AApr 5, 1994
Optimized write protocol for memory accesses utilizing row and column strobes
INTEL CORP23 citations92
US6012118AJan 4, 2000
Method and apparatus for performing bus operations in a computer system using deferred replies returned without using the address bus
INTEL CORP34 citations91
US5548734AAug 20, 1996
Equal length symmetric computer bus topology
INTEL CORP34 citations86
US5455957AOct 3, 1995
Method and apparatus for conducting bus transactions between two clock independent bus agents of a computer system using a transaction by transaction deterministic request/response protocol
INTEL CORP14 citations73
US5239638AAug 24, 1993
Two strobed memory access
INTEL CORP13 citations73
USRE40921ESep 22, 2009
Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system
INTEL CORP0 citations52