Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system

Abstract

A bus agent defers an ordered transaction if the transaction cannot be completed in order. When an ordered transaction is deferred, its visibility for the next ordered transaction is asserted if it can guarantee a sequential order of the ordered transaction and the next ordered transaction. This visibility indication allows the bus agent to proceed with the next ordered transaction without waiting for the completion status of the deferred transaction. The visibility indication provides fast processing of ordered transactions.

1. A method for efficient memory access in a computer system that includes an agent coupled to a chipset via a bus, the method comprising:
 issuing a first ordered transaction on the bus;  
 deferring processing of the first ordered transaction;  
 asserting a visibility signal by the chipset; and  
 issuing a second ordered transaction on the bus responsive to the visibility signal before the first ordered transaction is completed.  
 
     
     
       2. The method of  claim 1 , wherein the step of deferring comprises postponing the second ordered transaction if the visibility signal is negated. 
     
     
       3. The method of  claim 1  further comprises stalling the first ordered transaction if the first ordered transaction is not ready. 
     
     
       4. The method of  claim 1  further comprises accessing a cache line in a cache memory which is coupled to the bus if the cache line is one of the clean, shared, and modified states. 
     
     
       5. The method of  claim 3  further comprises postponing the second ordered transaction until the first ordered transaction is complete. 
     
     
       6. The method of  claim 4  further comprises completing the first ordered transaction. 
     
     
       7. A system comprising:
 a bus;  
 a chipset coupled to the bus, the chipset being configured to generate a defer signal and a visibility signal; and an agent coupled to the bus and the chipset, wherein the agent is configured to: 
 (I) issue a first ordered transaction on the bus; (ii) defer processing the first ordered transaction in response to the defer signal; (iii) issue a second ordered transaction on the bus in response to the visibility signal before the first ordered transaction is complete.  
 
 
     
     
       8. The system of  claim 7  wherein the agent postpones the second ordered transaction if the defer signal is asserted and the visibility signal is negated. 
     
     
       9. The system of  claim 7  wherein the agent issues the second transaction if the defer signal is asserted and the visibility signal is asserted. 
     
     
       10. An apparatus comprising:
   a chipset to receive a first ordered transaction and to generate a defer signal and a visibility signal indicating when a second ordered transaction can be issued before the first ordered transaction is complete.      
     
     
       11. The apparatus of  claim 10  further comprising
   an agent coupled to the chipset, wherein the agent is configured to: issue the first ordered transaction, defer processing the first ordered transaction in response to the defer signal, and issue a second ordered transaction in response to the visibility signal before the first ordered transaction is complete.      
     
     
       12. An apparatus comprising:
   an agent configured to: issue a first ordered transaction, receive a defer signal and a visibility signal, and issue the second ordered transaction in response to the defer signal and the visibility signal before the first ordered transaction is complete.      
     
     
       13. The apparatus of  claim 12 , the agent further configured to:
   defer processing of the first ordered transaction in response to the defer signal.      
     
     
       14. The apparatus of  claim 13  further comprising:
   a chipset to receive the first ordered transaction and to generate the defer signal and the visibility signal.      
     
     
       15. The apparatus of  claim 11  or  claim 13  wherein the agent postpones the second ordered transaction if the defer signal is asserted and the visibility signal is negated.  
     
     
       16. The apparatus of  claim 11  or  claim 13  wherein the agent issues the second transaction if the defer signal is asserted and the visibility signal is asserted.  
     
     
       17. A method for processing order- dependent memory access transactions comprising:      issuing a first ordered transaction;        receiving a defer signal;        deferring processing of the first ordered transaction responsive to the defer signal;        receiving a visibility signal; and        issuing a second ordered transaction responsive to the visibility signal before the first ordered transaction is completed.      
     
     
       18. The method of  claim 17  further comprising:
   postponing the second ordered transaction if the visibility signal is negated.      
     
     
       19. A method for processing order- dependent memory access transactions comprising:      receiving a first ordered transaction;        generating a defer signal to defer processing of the first ordered transaction;        generating a visibility signal to indicate when a second ordered transaction can be issued before the first ordered transaction is completed; and        receiving the second ordered transaction.      
     
     
       20. The method of  claim 19 , the visibility signal being generated also to postpone the second ordered transaction when the visibility signal is negated.  
     
     
       21. The method of  claim 17  or of  claim 19  further comprising:
   stalling the first ordered transaction if the first ordered transaction is not ready.      
     
     
       22. The method of  claim 17  or of  claim 19  further comprising:
   accessing a cache line in a cache memory if the cache line is one of the clean, shared, and modified states.      
     
     
       23. The method of  claim 21  further comprising:
   postponing the second ordered transaction until the first ordered transaction is complete.      
     
     
       24. The method of  claim 22  further comprising:
   completing the first ordered transaction.      
     
     
       25. A computer system comprising:
   a bus interface; and        a chipset to receive a first ordered transaction on the bus interface and to generate a defer signal and a visibility signal responsive to receiving the first ordered transaction when a second ordered transaction can be issued before the first ordered transaction is completed.      
     
     
       26. The system of  claim 25  wherein the defer signal is asserted and the visibility signal is negated to postpone a second ordered transaction.  
     
     
       27. The computer system of  claim 25  further comprising:
   an agent coupled to the chipset to: issue the first ordered transaction, defer processing the first ordered transaction in response to the defer signal, and issue the second ordered transaction in response to the visibility signal before the first ordered transaction is complete.      
     
     
       28. The system of  claim 27  wherein the defer signal is asserted and the visibility signal is asserted to cause the agent to issue the second ordered transaction before the first ordered transaction is complete.