Inventor · disambiguated record
William S. Wu
Also filed as: WU WILLIAM · WU WILLIAM S · WU WILLIAM S F
33 granted patents·3 pending applications·1,021 citations·filing 1994–2013
98Inventor score
Top patents by PatentIndex Score
36 records- 0195US8244960B2Non-volatile memory and method with write cache partition management methodsPALEY ALEXANDER·Filed 2009·Granted Aug 14, 2012·65 cites·12 claims
- 0295US8094500B2Non-volatile memory and method with write cache partitioningPALEY ALEXANDER·Filed 2009·Granted Jan 10, 2012·68 cites·20 claims
- 0394US9176864B2Non-volatile memory and method having block management with hot/cold data sortingGOROBETS SERGEY ANATOLIEVICH·Filed 2012·Granted Nov 3, 2015·81 cites·32 claims
- 0490US8626986B2Pre-emptive garbage collection of memory blocksWU WILLIAM·Filed 2010·Granted Jan 7, 2014·17 cites·18 claims
- 0588US8700840B2Nonvolatile memory with write cache having flush/eviction methodsPALEY ALEXANDER·Filed 2009·Granted Apr 15, 2014·22 cites·24 claims
- 0688US5822767AMethod and apparartus for sharing a signal line between agentsINTEL CORP·Filed 1997·Granted Oct 13, 1998·109 cites·11 claims
- 0783US6112016AMethod and apparatus for sharing a signal line between agentsINTEL CORP·Filed 1997·Granted Aug 29, 2000·83 cites·16 claims
- 0882US9104327B2Fast translation indicator to reduce secondary address table checks in a memory deviceGOROBETS SERGEY ANATOLIEVICH·Filed 2012·Granted Aug 11, 2015·7 cites·20 claims
- 0981US5809340AAdaptively generating timing signals for access to various memory devices based on stored profilesPACKARD BELL NEC·Filed 1997·Granted Sep 15, 1998·99 cites·5 claims
- 1078US9070449B2Defective block managementSANDISK TECHNOLOGIES INC·Filed 2013·Granted Jun 30, 2015·6 cites·24 claims
- 1172US5906001AMethod and apparatus for performing TLB shutdown operations in a multiprocessor system without invoking interrup handler routinesINTEL CORP·Filed 1996·Granted May 18, 1999·61 cites·16 claims
- 1270US8848445B2System and method for minimizing write amplification while maintaining sequential performance using logical group striping in a multi-bank systemSPROUSE STEVEN T·Filed 2012·Granted Sep 30, 2014·3 cites·14 claims
- 1369US6263397B1Mechanism for delivering interrupt messagesINTEL CORP·Filed 1998·Granted Jul 17, 2001·51 cites·36 claims
- 1468US5651137AScalable cache attributes for an input/output busINTEL CORP·Filed 1995·Granted Jul 22, 1997·42 cites·24 claims
- 1565US5919254AMethod and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple processing systemINTEL CORP·Filed 1997·Granted Jul 6, 1999·47 cites·18 claims
- 1664US9235530B2Method and system for binary cache cleanupWU WILLIAM·Filed 2010·Granted Jan 12, 2016·2 cites·28 claims
- 1763US6598103B2Transmission of signals synchronous to a common clock and transmission of data synchronous to strobes in a multiple agent processing systemINTEL CORP·Filed 2001·Granted Jul 22, 2003·8 cites·132 claims
- 1863US6266719B1High-throughput interface between a system memory controller and a peripheral deviceINTEL CORP·Filed 2000·Granted Jul 24, 2001·6 cites·5 claims
- 1962US9063862B2Expandable data cacheWU WILLIAM·Filed 2011·Granted Jun 23, 2015·1 cites·26 claims
- 2061US7039750B1On-chip switch fabricPLX TECHNOLOGY INC·Filed 2001·Granted May 2, 2006·14 cites·40 claims
- 2161US5961621AMechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined systemINTEL CORP·Filed 1997·Granted Oct 5, 1999·32 cites·9 claims
- 2259US6434692B2High-throughput interface between a system memory controller and a peripheral deviceINTEL CORP·Filed 2001·Granted Aug 13, 2002·4 cites·33 claims
- 2358US6012118AMethod and apparatus for performing bus operations in a computer system using deferred replies returned without using the address busINTEL CORP·Filed 1997·Granted Jan 4, 2000·34 cites·39 claims
- 2458US5848279AMechanism for delivering interrupt messagesINTEL CORP·Filed 1996·Granted Dec 8, 1998·30 cites·6 claims
- 2557US5964856AMechanism for data strobe pre-driving during master changeover on a parallel busINTEL CORP·Filed 1997·Granted Oct 12, 1999·34 cites·8 claims
- 2656US6336159B1Method and apparatus for transferring data in source-synchronous protocol and transferring signals in common clock protocol in multiple agent processing systemINTEL CORP·Filed 1998·Granted Jan 1, 2002·27 cites·191 claims
- 2753US6006291AHigh-throughput interface between a system memory controller and a peripheral deviceINTEL CORP·Filed 1997·Granted Dec 21, 1999·18 cites·9 claims
- 2851US6035436AMethod and apparatus for fault on use data error handlingINTEL CORP·Filed 1997·Granted Mar 7, 2000·26 cites·12 claims
- 2944USRE40921EMechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined systemINTEL CORP·Filed 2001·Granted Sep 22, 2009·0 cites·28 claims
- 3043US2012297121A1Non-Volatile Memory and Method with Small Logical Groups Distributed Among Active SLC and MLC Memory PartitionsGOROBETS SERGEY ANATOLIEVICH·Filed 2012·Application pending·0 cites
- 3142US6047355ASymmetric multiprocessing system with unified environment and distributed system functionsINTEL CORP·Filed 1997·Granted Apr 4, 2000·8 cites·13 claims
- 3240US2014281132A1Method and system for ram cache coalescingBUNDUKIN MARIELLE·Filed 2013·Application pending·0 cites
- 3339US5522069ASymmetric multiprocessing system with unified environment and distributed system functionsZENITH DATA SYSTEMS CORP·Filed 1994·Granted May 28, 1996·7 cites·1 claims
- 3437US2011153912A1Maintaining Updates of Multi-Level Non-Volatile Memory in Binary Non-Volatile MemoryGOROBETS SERGEY ANATOLIEVICH·Filed 2009·Application pending·0 cites
- 3533US6167468AHigh-throughput interface between a system memory controller and a peripheral deviceINTEL CORP·Filed 1999·Granted Dec 26, 2000·3 cites·7 claims
- 3633US5951663AMethod and apparatus for tracking bus transactionsINTEL CORP·Filed 1997·Granted Sep 14, 1999·6 cites·14 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →