Mechanism for data strobe pre-driving during master changeover on a parallel bus

Abstract

In a microprocessor system having a bus clock running at a bus clock rate, a method for reducing an idle interval between a first data transfer and a second data transfer, the method comprising the steps of: providing a first strobe signal and a second strobe signal for synchronizing said first and second data transfers with the bus clock; a pre-driving the first strobe signal before the first data transfer, the first strobe signal running at the bus clock rate during the first data transfer; and pre-driving one of the first and second strobe signals before the second data transfer, said one of the first and second strobe signals running at the bus clock rate during the second data transfer.

What is claimed is: 
     
       1. In a microprocessor system having a bus clock running at a bus clock rate, a method for reducing an idle interval between a first data transfer and a second data transfer, the method comprising the steps of: providing a first strobe signal and a second strobe signal for synchronizing said first and second data transfers with the bus clock, the first and second strobe signals clocking data in the first and second data transfers, respectively;   pre-driving the first strobe signal before the first data transfer, the first strobe signal running at the bus clock rate during the first data transfer; and   pre-driving one of the first and second strobe signals before the second data transfer, said one of the first and second strobe signals running at the bus clock rate during the second data transfer.   
     
     
       2. The method of claim 1 wherein the step of pre-driving one of the first and second strobe signals pre-drives the first strobe signal if said idle interval is equal to or larger than two clock cycles of said bus clock. 
     
     
       3. The method of claim 1 wherein the step of pre-driving one of the first and second strobe signals pre-drives the second strobe signal if said idle interval is less than two clock cycles of said bus clock. 
     
     
       4. The method of claim I wherein said first data transfer is requested by a first bus agent and the second data transfer is requested by a second bus agent. 
     
     
       5. The method of claim 4 wherein said idle interval is caused by a changeover of mastership between said first and second bus agents. 
     
     
       6. A computer system comprising: a bus having a bus clock, said bus comprising a data bus, said bus providing a first strobe signal and a second strobe signal, the first and second strobe signals clocking data in first and second data transfers, respectively;   a first bus agent coupled to said bus for initiating the first data transfer, said first data transfer being pre-driven by said first strobe signal;   a second bus agent coupled to said bus for initiating the second data transfer, said second data transfer being pre-driven by one of said first and second strobe signals during an idle interval between said first and second data transfers.   
     
     
       7. The computer system of claim 6 wherein said second data transfer is pre-driven by the first strobe signal if said idle interval is equal to or larger than two clock cycles of said bus clock. 
     
     
       8. The computer system of claim 6 wherein said second data transfer is pre-driven by the second strobe signal if said idle interval is less than two clock cycles of said bus clock.