Inventor
WU WILLIAM S
US23 patents
⚠️ This page may combine multiple inventors who share the name “WU WILLIAM S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
16 patentsUS5906001AMay 18, 1999
Method and apparatus for performing TLB shutdown operations in a multiprocessor system without invoking interrup handler routines
INTEL CORP61 citations96
US6263397B1Jul 17, 2001
Mechanism for delivering interrupt messages
INTEL CORP51 citations93
US6006291ADec 21, 1999
High-throughput interface between a system memory controller and a peripheral device
INTEL CORP18 citations92
US5961621AOct 5, 1999
Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system
INTEL CORP32 citations92
US5848279ADec 8, 1998
Mechanism for delivering interrupt messages
INTEL CORP30 citations92
US6336159B1Jan 1, 2002
Method and apparatus for transferring data in source-synchronous protocol and transferring signals in common clock protocol in multiple agent processing system
INTEL CORP27 citations91
US6012118AJan 4, 2000
Method and apparatus for performing bus operations in a computer system using deferred replies returned without using the address bus
INTEL CORP34 citations91
US5919254AJul 6, 1999
Method and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple processing system
INTEL CORP47 citations91
US6035436AMar 7, 2000
Method and apparatus for fault on use data error handling
INTEL CORP26 citations89
US5964856AOct 12, 1999
Mechanism for data strobe pre-driving during master changeover on a parallel bus
INTEL CORP34 citations89
US6434692B2Aug 13, 2002
High-throughput interface between a system memory controller and a peripheral device
INTEL CORP4 citations73
US6266719B1Jul 24, 2001
High-throughput interface between a system memory controller and a peripheral device
INTEL CORP6 citations73
US6047355AApr 4, 2000
Symmetric multiprocessing system with unified environment and distributed system functions
INTEL CORP8 citations73
US6598103B2Jul 22, 2003
Transmission of signals synchronous to a common clock and transmission of data synchronous to strobes in a multiple agent processing system
INTEL CORP8 citations72
US6167468ADec 26, 2000
High-throughput interface between a system memory controller and a peripheral device
INTEL CORP3 citations62
USRE40921ESep 22, 2009
Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system
INTEL CORP0 citations52
PALEY ALEXANDER
3 patentsUS8244960B2Aug 14, 2012
Non-volatile memory and method with write cache partition management methods
PALEY ALEXANDER65 citations96
US8094500B2Jan 10, 2012
Non-volatile memory and method with write cache partitioning
PALEY ALEXANDER68 citations96
US8700840B2Apr 15, 2014
Nonvolatile memory with write cache having flush/eviction methods
PALEY ALEXANDER22 citations91