Inventor
JAYAKUMAR MUTHURAJAN
US15 patents
Patents
15 patentsUS6108781AAug 22, 2000
Bootstrap processor selection architecture in SMP system
INTEL CORP71 citations96
US5904733AMay 18, 1999
Bootstrap processor selection architecture in SMP systems
INTEL CORP53 citations96
US6021458AFeb 1, 2000
Method and apparatus for handling multiple level-triggered and edge-triggered interrupts
INTEL CORP54 citations93
US6292906B1Sep 18, 2001
Method and apparatus for detecting and compensating for certain snoop errors in a system with multiple agents having cache memories
INTEL CORP62 citations92
US5961621AOct 5, 1999
Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system
INTEL CORP32 citations92
US5889978AMar 30, 1999
Emulation of interrupt control mechanism in a multiprocessor system
INTEL CORP34 citations92
US5848279ADec 8, 1998
Mechanism for delivering interrupt messages
INTEL CORP30 citations92
US5511200AApr 23, 1996
Method and apparatus for providing an enhanced programmable priority interrupt controller
INTEL CORP38 citations92
US6260091B1Jul 10, 2001
Method and apparatus for performing out-of-order bus operations in which an agent only arbitrates for use of a data bus to send data with a deferred reply
INTEL CORP19 citations91
US6012118AJan 4, 2000
Method and apparatus for performing bus operations in a computer system using deferred replies returned without using the address bus
INTEL CORP34 citations91
US5964856AOct 12, 1999
Mechanism for data strobe pre-driving during master changeover on a parallel bus
INTEL CORP34 citations89
US6298410B1Oct 2, 2001
Apparatus and method for initiating hardware priority management by software controlled register access
INTEL CORP33 citations88
US5481725AJan 2, 1996
Method for providing programmable interrupts for embedded hardware used with programmable interrupt controllers
INTEL CORP42 citations85
US5951663ASep 14, 1999
Method and apparatus for tracking bus transactions
INTEL CORP6 citations72
USRE40921ESep 22, 2009
Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system
INTEL CORP0 citations52