Inventor

Joseph Praveen

US25 patents

⚠️ This page may combine multiple inventors who share the name “Joseph Praveen”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

Joseph Praveen

IBM

Inverse tone direct print EUV lithography enabled by selective material deposition

Staggered stacked vertical crystalline semiconducting channels

Magnetoresistive random access memory thin film transistor unit cell

Vertically stacked fin semiconductor devices

Airgap isolation for back-end-of-the-line semiconductor interconnect structure with top via

Transistor having wrap-around source/drain contacts and under-contact spacers

Staggered stacked vertical crystalline semiconducting channels

Inverse tone pillar printing method using organic planarizing layer pillars

Bilayer hardmask for direct print lithography

Semiconductor structure with fully aligned vias

Transistor having wrap-around source/drain contacts and under-contact spacers

Inverse tone pillar printing method using polymer brush grafts

Vertically stacked fin semiconductor devices

Semiconductor device with multiple threshold voltages

Semiconductor device with multiple threshold voltages

Dielectric structure to prevent hard mask erosion

Approach to prevent collapse of high aspect ratio Fin structures for vertical transport Fin field effect transistor devices

Controlling gate length of vertical transistors

Semiconductor fin length variability control

CISCO TECH INC

Charging filtering function

Network slice based billing

Configurable distribution of network device usage data based on rules

UNIV TEXAS

Fabricating large area multi-tier nanostructures

Fabricating large area multi-tier nanostructures

Fabricating large area multi-tier nanostructures