Inventor

REARICK JEFFREY R

US22 patents

⚠️ This page may combine multiple inventors who share the name “REARICK JEFFREY R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

REARICK JEFFREY R

AGILENT TECHNOLOGIES INC

Systems and methods for facilitating automated test equipment functionality within integrated circuits

Systems and methods for testing receiver terminations in integrated circuits

Systems and methods for facilitating driver strength testing of integrated circuits

Systems and methods for facilitating testing of pad receivers of integrated circuits

Delay-locked loop and a method of testing a delay-locked loop

Method and apparatus for an embedded time domain reflectometry test

Testing target resistances in circuit assemblies

Systems and methods for facilitating testing of pad drivers of integrated circuits

Systems and methods for facilitating testing of pad receivers of integrated circuits

Systems and methods for facilitating testing of pad receivers of integrated circuits

Systems and methods for facilitating automated test equipment functionality within integrated circuits

AVAGO TECHNOLOGIES GENERAL IP

Circuit and method for comparing circuit performance between functional and AC scan testing in an integrated circuit (IC)

Method for determining the impact on test coverage of scan chain parallelization by analysis of a test set for independently accessible flip-flops

Delay-locked loop and a method of testing a delay-locked loop

System and method for automatic masking of compressed scan chains with unbalanced lengths

Method and apparatus for enabling a user to determine whether a defective location in a memory device has been remapped to a redundant memory portion

Programmable hysteresis for boundary-scan testing

Delay-locked loop and a method of testing a delay-locked loop

Apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC)

Apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC)

HEWLETT PACKARD CO

Test pattern generator having improved test sequence compaction

REARICK JEFFREY R

Systems and methods for facilitating testing of pads of integrated circuits