Circuit and method for comparing circuit performance between functional and AC scan testing in an integrated circuit (IC)

Abstract

A circuit and method for determining operating speed of a clock associated with an integrated circuit (IC), includes an IC logic element, a scan chain, and a calibration circuit including a first plurality of flip-flops and a combinational delay line. The calibration circuit operates in a functional test mode and in a scan test mode to determine a clock signal delay between the functional test mode and the scan test mode.

1. A circuit for determining operating speed of a clock associated with an integrated circuit (IC), comprising:
 an IC logic element located on the integrated circuit; 
 a scan chain located on the integrated circuit; and 
 a calibration circuit located on the integrated circuit and coupled to the IC logic element and to the scan chain, the calibration circuit comprising a first plurality of flip-flops and a combinational delay line, in which the calibration circuit operates in a functional test mode and in a scan test mode to determine a clock signal delay between the functional test mode and the scan test mode by measuring a difference in clock speed caused by power supply voltage drop between functional test mode and scan test mode and wherein the calibration circuit continuously compares a delay of the combinational delay line with a clock period of the clock signal, in which a digital delay provided by the combinational delay line is dynamically reconfigurable and in which the digital delay is used to choose a scan test frequency that tests the IC at a designed clock speed. 
 
     
     
       2. The circuit of  claim 1 , further comprising:
 a second plurality of flip-flops associated with the combinational delay line, the second plurality of flip-flops configured to provide a selectable delay through the combinational delay line. 
 
     
     
       3. The circuit of  claim 2 , in which the selectable delay is binary weighted. 
     
     
       4. The circuit of  claim 2 , further comprising a state machine configured to automatically determine the selectable delay. 
     
     
       5. A method for comparing integrated circuit (IC) performance in functional test mode and in scan test mode, comprising:
 operating a clock located on the IC at a frequency (f TARGET ) at which IC operation is sought to be determined; 
 loading a beginning delay value into a calibration circuit located on the IC; 
 functional testing the IC to determine a test delay value corresponding to a functional test pass/fail boundary; 
 enabling scan test of the IC; 
 loading the test delay value into the calibration circuit; 
 selecting a second clock frequency; 
 applying two clock cycles at the selected second clock frequency; 
 scan testing the IC using the test delay value to determine the highest clock frequency (f SCAN ) at which the IC passes the scan test; and 
 determining a delay within the selected clock frequency by comparing the difference between f SCAN  and f TARGET  by measuring a difference in clock speed caused by power supply voltage drop between functional test mode and scan test mode and continuously comparing the test delay value with a clock period of the clock, in which the test delay is a digital delay value and is dynamically reconfigurable and in which the test delay value is used to choose a scan test frequency that tests the IC at a designed clock speed. 
 
     
     
       6. The method of  claim 5 , in which the delay value is selectable using binary weighting. 
     
     
       7. The method of  claim 6 , further comprising using a state machine to automatically determine the selectable delay value. 
     
     
       8. The method of  claim 5 , in which a first clock pulse is implemented using a last shift of a scan chain associated with the IC to launch a transition, and a second clock pulse is implemented to capture data. 
     
     
       9. A method for comparing integrated circuit (IC) performance in a functional test mode and in a scan test mode, comprising:
 operating a clock located on the IC at a target frequency at which IC operation is sought to be determined (f SCAN ); 
 loading a beginning delay value into a calibration circuit located on the IC; 
 scan testing the IC to determine a calibration delay value corresponding to a scan test pass/fail boundary by applying two clock cycles at the selected clock frequency; 
 enabling functional test of the IC; 
 loading the calibration delay value into the calibration circuit; 
 functional testing the IC using the calibration delay value to determine the highest clock frequency (f FUNCTIONAL ) at which the IC passes the functional test; and 
 determining a clock period elongation by comparing the difference between f SCAN  and f FUNCTIONAL  by measuring a difference in clock speed caused by power supply voltage drop between functional test mode and scan test mode and continuously comparing the test delay value with a clock period of the clock, in which a digital delay provided by the combinational delay line is dynamically reconfigurable and in which the digital delay is used to choose a scan test frequency that tests the IC at a designed clock speed. 
 
     
     
       10. The method of  claim 9 , in which the delay value is selectable using binary weighting. 
     
     
       11. The method of  claim 10 , further comprising using a state machine to automatically determine the selectable delay value. 
     
     
       12. A method for comparing integrated circuit (IC) performance in functional test mode and in scan test mode, comprising:
 functional testing an IC to determine a delay value associated with a nominal clock frequency (f TARGET ); 
 scan testing the IC using the delay value to determine a scan test clock frequency (f SCAN ); and 
 determining a clock delay by taking the difference between f SCAN  and f TARGET  using a calibration circuit located on the IC by measuring a difference in clock speed caused by power supply voltage drop between functional test mode and scan test mode and continuously comparing a test delay with a clock period of the clock, in which the delay value is a digital delay and is dynamically reconfigurable and in which the delay value is used to choose a scan test frequency that tests the IC at a designed clock speed. 
 
     
     
       13. The method of  claim 12 , in which the delay value is binary selectable between a value of seven gate delays and 128 gate delays. 
     
     
       14. The method of  claim 12 , further comprising using a state machine to automatically determine the selectable delay value. 
     
     
       15. A method for comparing integrated circuit (IC) performance in functional test mode and in scan test mode, comprising:
 operating a clock located on the IC at a target frequency at which IC operation is sought to be determined (f TARGET ); 
 loading a beginning delay value into a calibration circuit located on the IC; 
 scan testing the IC to determine a calibration delay value d SCAN  corresponding to a scan test pass/fail boundary by applying two clock cycles at the selected clock frequency; 
 enabling functional test of the IC; 
 loading a beginning delay value into a calibration circuit associated with the IC; 
 functional testing the IC to determine a calibration delay value d FUNCTIONAL  corresponding to a functional test pass/fail boundary by applying a steady stream of clock cycles at the selected clock frequency; 
 determining the unit delay value D by dividing 1 by a product of f FUNCTIONAL  and d FUNCTIONAL ; and 
 determining a clock period elongation by multiplying D times the difference between d SCAN  and d FUNCTIONAL  by measuring a difference in clock speed caused by power supply voltage drop between functional test mode and scan test mode and continuously comparing the test delay value with a clock period of the clock, in which the test delay value is a digital delay and is dynamically reconfigurable and in which the test delay value is used to choose a scan test frequency that tests the IC at a designed clock speed. 
 
     
     
       16. The method of  claim 15 , further comprising using a state machine to automatically determine the selectable delay value.