Inventor

SODHI INDER M

US78 patents

⚠️ This page may combine multiple inventors who share the name “SODHI INDER M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SODHI INDER M

INTEL CORP

Controlling operating voltage of a processor

Controlling operating voltage of a processor

Controlling power delivery to a processor via a bypass

Controlling operating voltage of a processor

Method and apparatus for improved reliability and reduced power in a processor by automatic voltage control during processor idle states

Controlling operating voltage of a processor

Enabling a non-core domain to control memory bandwidth in a processor

Method, apparatus, and system for energy efficiency and energy conservation including autonomous hardware-based deep power down in devices

Controlling power delivery to a processor via a bypass

Controlling power delivery to a processor via a bypass

Controlling power delivery to a processor via a bypass

Dyanamically adapting a voltage of a clock generation circuit

Dyanamically adapting a voltage of a clock generation circuit

Common platform for one-level memory architecture and two-level memory architecture

System, method and apparatus for energy efficiency and energy conservation by configuring power management parameters during run time

Enabling a non-core domain to control memory bandwidth in a processor

Method, apparatus, and system for energy efficiency and energy conservation including autonomous hardware-based deep power down in devices

Enabling a non-core domain to control memory bandwidth in a processor

Controlling power delivery to a processor via a bypass

Method for booting a heterogeneous system and presenting a symmetric core view

Apparatus and method for heterogeneous processors mapping to virtual cores

Hetergeneous processor apparatus and method

Selective migration of workloads between heterogeneous compute elements based on evaluation of migration performance benefit and available energy and thermal budgets

Method, apparatus, and system for energy efficiency and energy conservation including autonomous hardware-based deep power down in devices

Common platform for one-level memory architecture and two-level memory architecture

APPLE INC

Supply voltage envelope detection

Current measurement for power converter circuits

Systems and methods for coherent power management

Systems and methods for coherent power management

Tracking power consumption using multiple sampling frequencies

Power management based on limiting hardware-forced power control

Multi-die power synchronization

Power management unit

Systems and methods for coherent power management

Systems and methods for coherent power management

Scalable, hierarchical power delivery system

Current measurement for power converter circuits

Power delivery reduction scheme for SoC

Scalable, hierarchical power delivery system

SODHI INDER M

Method, apparatus, and system for energy efficiency and energy conservation including autonomous hardware-based deep power down in devices

Execution context swap between heterogeneous functional hardware units

Method, apparatus, and system for energy efficiency and energy conservation including improved processor core deep power down exit latency by using register secondary uninterrupted power supply

Method, apparatus, and system for energy efficiency and energy conservation including dynamic cache sizing and cache operating voltage management for optimal power performance

DAEDALUS PRIME LLC

Controlling operating voltage of a processor

Controlling operating frequency of a processor

Controlling operating voltage of a processor

ANANTHAKRISHNAN AVINASH N

Enabling a non-core domain to control memory bandwidth in a processor

RAY JOYDEEP

Common platform for one-level memory architecture and two-level memory architecture

WELLS RYAN D

Method, apparatus, and system for energy efficiency and energy conservation including enhanced temperature based voltage control

TAHOE RES LTD

Controlling power delivery to a processor via a bypass