P

Inventor

WISE RICHARD

US60 patents
⚠️ This page may combine multiple inventors who share the name “WISE RICHARD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LAM RES CORP

28 patents
US9824893B1Nov 21, 2017

Tin oxide thin film spacers in semiconductor device manufacturing

LAM RES CORP442 citations98
US11322351B2May 3, 2022

Tin oxide films in semiconductor device manufacturing

LAM RES CORP15 citations94
US11257674B2Feb 22, 2022

Eliminating yield impact of stochastics in lithography

LAM RES CORP15 citations94
US11031245B2Jun 8, 2021

Tin oxide thin film spacers in semiconductor device manufacturing

LAM RES CORP21 citations94
US10796912B2Oct 6, 2020

Eliminating yield impact of stochastics in lithography

LAM RES CORP18 citations94
US10546748B2Jan 28, 2020

Tin oxide films in semiconductor device manufacturing

LAM RES CORP25 citations94
US10269566B2Apr 23, 2019

Etching substrates using ale and selective deposition

LAM RES CORP15 citations94
US10197908B2Feb 5, 2019

Photoresist design layout pattern proximity correction through fast edge placement error prediction via a physics-based etch profile modeling framework

LAM RES CORP27 citations94
US11183383B2Nov 23, 2021

Tin oxide thin film spacers in semiconductor device manufacturing

LAM RES CORP16 citations93
US12094711B2Sep 17, 2024

Tin oxide films in semiconductor device manufacturing

LAM RES CORP5 citations86
US11784047B2Oct 10, 2023

Tin oxide thin film spacers in semiconductor device manufacturing

LAM RES CORP10 citations86
US10534257B2Jan 14, 2020

Layout pattern proximity correction through edge placement error prediction

LAM RES CORP17 citations86
US12278125B2Apr 15, 2025

Integrated dry processes for patterning radiation photoresist patterning

LAM RES CORP8 citations85
US11355353B2Jun 7, 2022

Tin oxide mandrels in patterning

LAM RES CORP15 citations85
US12183604B2Dec 31, 2024

Integrated dry processes for patterning radiation photoresist patterning

LAM RES CORP9 citations84
US10685836B2Jun 16, 2020

Etching substrates using ALE and selective deposition

LAM RES CORP10 citations84
US10585347B2Mar 10, 2020

Photoresist design layout pattern proximity correction through fast edge placement error prediction via a physics-based etch profile modeling framework

LAM RES CORP9 citations84
US9984858B2May 29, 2018

ALE smoothness: in and outside semiconductor industry

LAM RES CORP10 citations84
US9922839B2Mar 20, 2018

Low roughness EUV lithography

LAM RES CORP6 citations84
US12437995B2Oct 7, 2025

Tin oxide films in semiconductor device manufacturing

LAM RES CORP1 citations75
US12417916B2Sep 16, 2025

Tin oxide films in semiconductor device manufacturing

LAM RES CORP1 citations75
US12051589B2Jul 30, 2024

Tin oxide thin film spacers in semiconductor device manufacturing

LAM RES CORP6 citations75
US12183589B2Dec 31, 2024

Tin oxide mandrels in patterning

LAM RES CORP3 citations74
US12062538B2Aug 13, 2024

Atomic layer etch and selective deposition process for extreme ultraviolet lithography resist improvement

LAM RES CORP3 citations73
US11987876B2May 21, 2024

Chamfer-less via integration scheme

LAM RES CORP6 citations73
US10438807B2Oct 8, 2019

Low roughness EUV lithography

LAM RES CORP3 citations73
US10304659B2May 28, 2019

Ale smoothness: in and outside semiconductor industry

LAM RES CORP4 citations73
US12315727B2May 27, 2025

Eliminating yield impact of stochastics in lithography

LAM RES CORP0 citations62

IBM

13 patents
US7288482B2Oct 30, 2007

Silicon nitride etching methods

IBM260 citations95
US6541320B2Apr 1, 2003

Method to controllably form notched polysilicon gate structures

IBM32 citations92
US6461529B1Oct 8, 2002

Anisotropic nitride etch process with high selectivity to oxide and photoresist layers in a damascene etch scheme

IBM34 citations92
US6869542B2Mar 22, 2005

Hard mask integrated etch process for patterning of silicon oxide and other dielectric materials

IBM35 citations89
US8008160B2Aug 30, 2011

Method and structure for forming trench DRAM with asymmetric strap

IBM11 citations84
US7671421B2Mar 2, 2010

CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials

IBM8 citations84
US6511791B1Jan 28, 2003

Multiple exposure process for formation of dense rectangular arrays

IBM19 citations84
US7691701B1Apr 6, 2010

Method of forming gate stack and structure thereof

IBM16 citations83
US6090722AJul 18, 2000

Process for fabricating a semiconductor structure having a self-aligned spacer

IBM14 citations73
US7871893B2Jan 18, 2011

Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devices

IBM4 citations63
US7776695B2Aug 17, 2010

Semiconductor device structure having low and high performance devices of same conductive type on same substrate

IBM2 citations63
US8586431B2Nov 19, 2013

Three dimensional integration and methods of through silicon via creation

IBM3 citations62
US6806200B2Oct 19, 2004

Method of improving etch uniformity in deep silicon etching

IBM4 citations62

FAROOQ MUKTA G

4 patents

CHEN TZE-CHIANG

2 patents

(unassigned)

1 patent

TOKYO ELECTRON LTD

1 patent

SBH INC

1 patent

Showing the top 50 of 60 patents by PatentIndex Score.