Inventor

SATPATHY SUDHIR K

US52 patents

⚠️ This page may combine multiple inventors who share the name “SATPATHY SUDHIR K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SATPATHY SUDHIR K

INTEL CORP

Methods and apparatus to parallelize data decompression

Method and apparatus for accelerating canonical huffman encoding

Soft dark bit masking with integrated load modulation and burn-in induced destabilization for physically unclonable function keys

Double affine mapped S-box hardware accelerator

Method and apparatus for prefix decoding acceleration

Methods and apparatus to parallelize data decompression

Method and apparatus for decompression acceleration in multi-cycle decoder based platforms

Physically unclonable circuit having a programmable input for improved dark bit mask accuracy

Stable probing-resilient physically unclonable function (PUF) circuit

Method, apparatus and system for a source-synchronous circuit-switched network on a chip (NOC)

Method and apparatus to provide memory based physically unclonable functions

Adaptive speculative decoding

Unified hardware accelerator for symmetric-key ciphers

Methods and apparatus to parallelize data decompression

Efficient length limiting of compression codes

Random number generator that includes physically unclonable circuits

Multi-stage non-linearly cascaded physically unclonable function circuit

Methods and apparatus to parallelize data decompression

Energy-efficient bitcoin mining hardware accelerators

Hardware apparatuses and methods for data decompression

Optimized SHA-256 datapath for energy-efficient high-performance Bitcoin mining

Hybrid SM3 and SHA acceleration processors

Non-linear physically unclonable function (PUF) circuit with machine-learning attack resistance

Hardware accelerator for cryptographic hash operations

Random number generator

Composite field scaled affine transforms-based hardware accelerator

Efficient huffman decoder improvements

Instruction and logic for accelerated compressed data decoding

Stable probing-resilient physically unclonable function (PUF) circuit

Linear masking circuits for side-channel immunization of advanced encryption standard hardware

Methods and apparatus to parallelize data decompression

Methods and apparatus to parallelize data decompression

Method and apparatus for speculative decompression

System, apparatus and method for performing a plurality of cryptographic operations

Method and apparatus for energy efficient decompression using ordered tokens

Power side-channel attack resistant advanced encryption standard accelerator processor

System, apparatus and method for performing a plurality of cryptographic operations

Mixed-coordinate point multiplication

Unified integer and carry-less modular multiplier and a reduction circuit

Composite field scaled affine transforms-based hardware accelerator

Parallel computation techniques for accelerated cryptographic capabilities

Photon emission attack resistance driver circuits

Energy-efficient dual-rail keeperless domino datapath circuits

Power side-channel attack resistant advanced encryption standard accelerator processor

Method and apparatus for speculative decompression

SMS4 acceleration processors having encryption and decryption mapped on a same hardware

Threshold filtering of compressed domain data using steering vector

Threshold filtering of compressed domain data using steering vector

MATHEW SANU K

Using dark bits to reduce physical unclonable function (PUF) error rate without storing dark bits location

SATPATHY SUDHIR K

Hybrid CAM assisted deflate decompression accelerator