Inventor
NAGARAJAN SURESH
US16 patents
⚠️ This page may combine multiple inventors who share the name “NAGARAJAN SURESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
15 patentsUS10229735B1Mar 12, 2019
Block management for dynamic single-level cell buffers in storage devices
INTEL CORP57 citations96
US7246195B2Jul 17, 2007
Data storage management for flash memory devices
INTEL CORP10 citations76
US11237732B2Feb 1, 2022
Method and apparatus to improve write bandwidth of a block-based multi-level cell nonvolatile memory
INTEL CORP6 citations74
US10379782B2Aug 13, 2019
Host managed solid state drivecaching using dynamic write acceleration
INTEL CORP6 citations72
US11769557B2Sep 26, 2023
Techniques for preventing read disturb in NAND memory
INTEL CORP2 citations71
US10650886B2May 12, 2020
Block management for dynamic single-level cell buffers in storage devices
INTEL CORP2 citations71
US12014081B2Jun 18, 2024
Host managed buffer to store a logical-to physical address table for a solid state drive
INTEL CORP0 citations61
US11119672B2Sep 14, 2021
Dynamic single level cell memory controller
INTEL CORP1 citations61
US12094545B2Sep 17, 2024
Techniques for preventing read disturb in NAND memory
INTEL CORP0 citations60
US11783893B2Oct 10, 2023
Utilizing NAND buffer for DRAM-less multilevel cell programming
INTEL CORP0 citations52
US10996860B2May 4, 2021
Method to improve mixed workload performance on storage devices that use cached operations
INTEL CORP0 citations51
US12147286B2Nov 19, 2024
Power and thermal management in a solid state drive
INTEL CORP0 citations50
US12019558B2Jun 25, 2024
Logical to physical address indirection table in a persistent memory in a solid state drive
INTEL CORP0 citations45
US10877686B2Dec 29, 2020
Mass storage device with host initiated buffer flushing
INTEL CORP0 citations40
US7603531B2Oct 13, 2009
Use of a shutdown object to improve initialization performance
INTEL CORP0 citations39