Inventor

RAJENDRAN BIPIN

US64 patents

⚠️ This page may combine multiple inventors who share the name “RAJENDRAN BIPIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RAJENDRAN BIPIN

IBM

Phase change memory device and method of manufacture

Measurement method for reading multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition

Coding techniques for improving the sense margin in content addressable memories

Process for PCM integration with poly-emitter BJT as access device

High density content addressable memory using phase change devices

Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition

Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition

Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition

Multi-level cell programming of PCM by varying the reset amplitude

Reconfigurable and customizable general-purpose circuits for neural networks

Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices

Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices

Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices

Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices

Reconfigurable and customizable general-purpose circuits for neural networks

Phase change memory management

Thermally insulated phase change material cells

Phase change memory with finite annular conductive path

Method for fabrication of polycrystalline diodes for resistive memories

Method for fabrication of single crystal diodes for resistive memories

Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition

High density ternary content addressable memory

Method to create a uniformly distributed multi-level cell (MLC) bitstream from a non-uniform MLC bitstream

Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition

BREITWISCH MATTHEW J

Resistive memory devices having a not-and (NAND) structure

Area efficient neuromorphic system that connects a FET in a diode configuration, and a variable resistance material to junctions of neuron circuit blocks

Area efficient neuromorphic circuits using field effect transistors (FET) and variable resistance material

Phase change memory electrode with sheath for reduced programming current

Phase change memory device suitable for high temperature operation

Thermally insulated phase change material memory cells

Measurement method for reading multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition

MACRONIX INT CO LTD

Phase change memory cells having vertical channel access transistor and memory plane

Memory array with diode driver and method for fabricating the same

Polysilicon plug bipolar transistor for phase change memory

Phase change memory dynamic resistance test and manufacturing methods

RAJENDRAN BIPIN

Electronic synapses from stochastic binary memory devices

Electronic synapses from stochastic binary memory devices

Polysilicon emitter BJT access device for PCRAM

Polysilicon emitter BJT access device for PCRAM

BREZZO BERNARD V

Reconfigurable and customizable general-purpose circuits for neural networks

Reconfigurable and customizable general-purpose circuits for neural networks

FRIEDMAN DANIEL J

Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices

ELMEGREEN BRUCE G

Hardware analog-digital neural networks

BREITWISCH MATTHEW JOSEPH

System for electronic learning synapse with spike-timing dependent plasticity using phase change memory

LUNG HSIANG-LAN

Polysilicon pillar bipolar transistor with self-aligned memory element

SHIH YEN-HAO

Methods and apparatus for reducing defect bits in phase change memory

JACKSON BRYAN LAWRENCE

Producing spike-timing dependent plasticity in an ultra-dense synapse cross-bar array

CHEN TZE-CHIANG

PCM with poly-emitter BJT access devices

SCHROTT ALEJANDRO G

Nanoscale electrodes for phase change memory devices

HAPP THOMAS

Integrated circuit including vertical diode