Phase change memory cells having vertical channel access transistor and memory plane

Abstract

Memory devices are described along with methods for manufacturing. A memory device as described herein comprises a plurality of word lines overlying a plurality of bit lines, and a plurality of field effect transistors. Field effect transistors in the plurality of field effect transistors comprises a first terminal electrically coupled to a corresponding bit line in the plurality of bit lines, a second terminal overlying the first terminal, and a channel region separating the first and second terminals and adjacent a corresponding word line in the plurality of word lines. The corresponding word line acts as the gate of the field effect transistor. A dielectric separates the corresponding word line from the channel region. A memory plane comprises programmable resistance memory material electrically coupled to respective second terminals of the field effect transistors, and conductive material on the programmable resistance memory material and coupled to a common voltage.

1. A memory device comprising:
 a plurality of bit lines; 
 a plurality of word lines overlying the plurality of bit lines; 
 a plurality of field effect transistors, field effect transistors in the plurality of field effect transistors comprising: 
 a first terminal electrically coupled to a corresponding bit line in the plurality of bit lines; 
 a second terminal overlying the first terminal; 
 a channel region separating the first and second terminals and adjacent a corresponding word line in the plurality of word lines, the corresponding word line acting as a gate of the field effect transistor, and wherein the channel region has a top view cross-sectional channel area; 
 a dielectric separating the corresponding word line from the channel region; and 
 
       a memory plane comprising programmable resistance memory material electrically coupled to respective second terminals of the field effect transistors, and conductive material on the programmable resistance memory material and coupled to a common voltage, wherein the memory plane comprises a plurality of memory patches of programmable resistance memory material, memory patches in the plurality of memory patches having a top view cross-sectional patch area greater than or equal to ten times the top view cross-sectional channel area. 
     
     
       2. The device of  claim 1 , further comprising a plurality of vias within the word lines, respective vias having a sidewall surface surrounding the channel region of the corresponding field effect transistor. 
     
     
       3. The device of  claim 2 , wherein the first and second terminals and channel region of the field effect transistors form a stack extending through the corresponding via. 
     
     
       4. The device of  claim 1 , further comprising a plurality of electrodes electrically coupled to the respective second terminals of the field effect transistors. 
     
     
       5. The device of  claim 4 , further comprising a conductive cap comprising silicide on the second terminals of the field effect transistors, the plurality of electrodes extending through a second dielectric to contact top surfaces of respective conductive caps of the field effect transistors. 
     
     
       6. The device of  claim 5 , wherein the plurality of electrodes have respective top surfaces contacting the programmable resistance memory material of the memory plane, the top surfaces of the electrodes having a surface area less than that of top surfaces of the corresponding conductive caps. 
     
     
       7. The device of  claim 1 , wherein the programmable resistance memory material extends through openings in a second dielectric overlying the respective second terminals of the field effect transistors. 
     
     
       8. The device of  claim 1 , wherein the memory plane comprises a blanket layer of the programmable resistance memory material overlying the respective second terminals of the field effect transistors. 
     
     
       9. A method for manufacturing a memory device, the method comprising:
 forming a plurality of bit lines; 
 forming a plurality of word lines overlying the plurality of bit lines; 
 forming a plurality of field effect transistors, forming field effect transistors in the plurality of field effect transistors comprising: 
 forming a first terminal electrically coupled to a corresponding bit line in the plurality of bit lines; 
 forming a second terminal overlying the first terminal and acting as a drain or source; 
 forming a channel region separating the first and second terminals and adjacent a corresponding word line in the plurality of word lines, the corresponding word line acting as a gate of the field effect transistor, and wherein the channel region has a top view cross-sectional channel area; 
 
       forming a dielectric separating the corresponding word line from the channel region; and
 forming a memory plane comprising forming programmable resistance memory material electrically coupled to respective second terminals of the field effect transistors, and forming conductive material on the programmable resistance memory material and coupled to a common voltage, and wherein the memory plane comprises a plurality of memory patches of programmable resistance memory material, memory patches in the plurality of memory patches having a top view cross-sectional patch area greater than or equal to ten times the top view cross-sectional channel area. 
 
     
     
       10. The method of  claim 9 , further comprising forming a plurality of vias within the word lines, respective vias having a sidewall surface surrounding a channel region of a corresponding field effect transistor. 
     
     
       11. The method of  claim 10 , wherein the first and second terminals and channel region of the field effect transistors form a stack extending through the corresponding via. 
     
     
       12. The method of  claim 9 , further comprising forming a plurality of electrodes electrically coupled to the respective second terminals of the field effect transistors, wherein forming the programmable resistance memory material comprises forming the programmable resistance memory material contacting top surfaces of the electrodes. 
     
     
       13. The method of  claim 12 , further comprising forming a conductive cap comprising silicide on the second terminals of the field effect transistors, wherein forming the plurality of electrodes comprises forming the plurality of electrodes extending through a second dielectric to contact top surfaces of respective conductive caps of the field effect transistors. 
     
     
       14. The method of  claim 13 , wherein the plurality of electrodes have respective top surfaces contacting the programmable resistance memory material of the memory plane, the top surfaces of the electrodes having a surface area less than that of top surfaces of the corresponding conductive caps. 
     
     
       15. The method of  claim 9 , wherein forming the programmable resistance memory material comprises forming the programmable resistance memory material within openings in a second dielectric overlying the respective second terminals of the field effect transistors. 
     
     
       16. The method of  claim 9 , wherein forming the memory plane comprises:
 forming a blanket layer of the programmable resistance memory material; and 
 forming a blanket layer of the conductive material on the blanket layer of the programmable resistance memory material. 
 
     
     
       17. The method of  claim 9 , wherein the forming the plurality of word lines and the forming the plurality of field effect transistors comprise:
 forming a second dielectric on the plurality of bit lines; 
 forming the plurality of word lines on the second dielectric; 
 forming a plurality of openings in the word lines to expose portions of a top surface of the plurality of bit lines; 
 forming the dielectric on sidewalls of the openings; and 
 forming the first and second terminals and the channel regions of the respective field effect transistors within corresponding openings in the plurality of openings, the first terminals contacting the top surface of the plurality of bit lines. 
 
     
     
       18. The method of  claim 17 , wherein the forming the dielectric along sidewalls of the openings comprises:
 forming the dielectric on the sidewalls of the openings and on the exposed portions of the top surface of the plurality of bit lines; and 
 forming sacrificial material on the layer of the dielectric; 
 anisotropically etching the dielectric and the sacrificial material to expose portions of the top surface of the plurality of bit lines; and 
 removing remaining portions of the sacrificial material. 
 
     
     
       19. The method of  claim 17 , wherein the forming the first and second terminals and the channel regions of the respective field effect transistors within corresponding openings in the plurality of openings comprises:
 performing an epitaxial process within the plurality of openings to form doped pillars on the top surfaces of the plurality of bit lines, the doped pillars having a first conductivity type; 
 implanting dopants having a second conductivity type within a portion of the doped pillars, wherein remaining portions of the doped pillars having the first conductivity type are the first terminals; and 
 implanting dopants having the first conductivity type within an upper portion of the doped pillars to form the second terminals, wherein remaining portions of the doped pillars having the second conductivity type are the channel regions. 
 
     
     
       20. The method of  claim 9 , wherein the forming the plurality of word lines and the forming the plurality of field effect transistors comprise:
 forming first terminal material on the plurality of bit lines, channel region material on the first terminal material, and second terminal material on the channel region material; 
 patterning the first and second terminal materials and the channel region material to form a plurality of stacks on the plurality of bit lines; 
 forming the dielectric on outer surfaces of the stacks; 
 depositing word line material surrounding the dielectric; and 
 patterning the word line material to form the plurality of word lines.