Inventor · disambiguated record
Ajay Baranwal
Also filed as: BARANWAL AJAY
11 granted patents·6 pending applications·24 citations·filing 2018–2025
85Inventor score
Top patents by PatentIndex Score
17 records- 0193US11250199B1Methods and systems for generating shape data for electronic designsCENTER FOR DEEP LEARNING IN ELECTRONICS MFG INC·Filed 2020·Granted Feb 15, 2022·8 cites·19 claims
- 0292US10592634B1Systems and methods for automatic handling of engineering design parameter violationsANSYS INC·Filed 2018·Granted Mar 17, 2020·13 cites·20 claims
- 0385US11823423B2Methods and systems for compressing shape data for electronic designsCENTER FOR DEEP LEARNING IN ELECTRONICS MFG INC·Filed 2021·Granted Nov 21, 2023·1 cites·25 claims
- 0484US12287567B2Method and system for reticle enhancement technologyD2S INC·Filed 2024·Granted Apr 29, 2025·0 cites·22 claims
- 0582US11847400B2Methods and systems for generating shape data for electronic designsCENTER FOR DEEP LEARNING IN ELECTRONICS MFG INC·Filed 2021·Granted Dec 19, 2023·1 cites·21 claims
- 0679US11921420B2Method and system for reticle enhancement technologyD2S INC·Filed 2023·Granted Mar 5, 2024·0 cites·18 claims
- 0777US11182929B2Methods and systems for compressing shape data for electronic designsCENTER FOR DEEP LEARNING IN ELECTRONICS MFG INC·Filed 2020·Granted Nov 23, 2021·1 cites·15 claims
- 0876US12288022B2Methods and systems for generating shape data for electronic designsCENTER FOR DEEP LEARNING IN ELECTRONICS MFG INC·Filed 2023·Granted Apr 29, 2025·0 cites·21 claims
- 0976US2024037803A1Methods and systems for compressing shape data for electronic designsCENTER FOR DEEP LEARNING IN ELECTRONICS MFG INC·Filed 2023·Application pending·0 cites
- 1072US2025237940A1Method and system for reticle enhancement technologyD2S INC·Filed 2025·Application pending·0 cites
- 1172US2025292389A1Method for computational metrology and inspection for patterns to be manufactured on a substrateD2S INC·Filed 2025·Application pending·0 cites
- 1272US2024346669A1Methods and systems for registering images for electronic designsCENTER FOR DEEP LEARNING IN ELECTRONICS MFG INC·Filed 2024·Application pending·0 cites
- 1368US12340495B2Method for computational metrology and inspection for patterns to be manufactured on a substrateD2S INC·Filed 2022·Granted Jun 24, 2025·0 cites·11 claims
- 1466US12045996B2Methods and systems for registering images for electronic designsCENTER FOR DEEP LEARNING IN ELECTRONICS MFG INC·Filed 2021·Granted Jul 23, 2024·0 cites·15 claims
- 1564US2024086607A1Modeling of a design in reticle enhancement technologyD2S INC·Filed 2023·Application pending·0 cites
- 1654US11264206B2Methods and systems for forming a pattern on a surface using multi-beam charged particle beam lithographyD2S INC·Filed 2019·Granted Mar 1, 2022·0 cites·14 claims
- 1745US2020057807A1Systems and methods providing a cognitive augmented memory networkNIRVEDA COGNITION INC·Filed 2019·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Ajay Baranwal files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →