Inventor · disambiguated record
Albert J. Loper
Also filed as: LOPER ALBERT J · LOPER ALBERT JOHN · LOPER JR ALBERT J
35 granted patents·1 pending application·908 citations·filing 1995–2015
98Inventor score
Technology areasG06F
Top patents by PatentIndex Score
36 records- 0189US5764969AMethod and system for enhanced management operation utilizing intermixed user level and supervisory level instructions with partial concept synchronizationIBM·Filed 1995·Granted Jun 9, 1998·168 cites·12 claims
- 0282US8234450B2Efficient data prefetching in the presence of load hitsGLOVER CLINTON THOMAS·Filed 2010·Granted Jul 31, 2012·6 cites·8 claims
- 0381US7191320B2Apparatus and method for performing a detached load operation in a pipeline microprocessorVIA TECH INC·Filed 2004·Granted Mar 13, 2007·33 cites·49 claims
- 0478US7480685B2Apparatus and method for generating packed sum of absolute differencesVIA TECH INC·Filed 2007·Granted Jan 20, 2009·7 cites·11 claims
- 0575US5870616ASystem and method for reducing power consumption in an electronic circuitIBM·Filed 1996·Granted Feb 9, 1999·68 cites·22 claims
- 0672US5822758AMethod and system for high performance dynamic and user programmable cache arbitrationIBM·Filed 1996·Granted Oct 13, 1998·65 cites·43 claims
- 0772US5752014AAutomatic selection of branch prediction methodology for subsequent branch instruction based on outcome of previous branch predictionIBM·Filed 1996·Granted May 12, 1998·60 cites·21 claims
- 0870US9652400B2Fully associative cache memory budgeted by memory access typeVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted May 16, 2017·2 cites·21 claims
- 0970US8489823B2Efficient data prefetching in the presence of load hitsGLOVER CLINTON THOMAS·Filed 2012·Granted Jul 16, 2013·2 cites·10 claims
- 1068US8051116B2Apparatus and method for generating packed sum of absolute differencesVIA TECH INC·Filed 2008·Granted Nov 1, 2011·3 cites·17 claims
- 1167US5805907ASystem and method for reducing power consumption in an electronic circuitIBM·Filed 1996·Granted Sep 8, 1998·48 cites·12 claims
- 1263US8543765B2Efficient data prefetching in the presence of load hitsGLOVER CLINTON THOMAS·Filed 2012·Granted Sep 24, 2013·1 cites·16 claims
- 1363US6061781AConcurrent execution of divide microinstructions in floating point unit and overflow detection microinstructions in integer unit for integer divideIP FIRST LLC·Filed 1998·Granted May 9, 2000·43 cites·28 claims
- 1463US5898864AMethod and system for executing a context-altering instruction without performing a context-synchronization operation within high-performance processorsIBM·Filed 1997·Granted Apr 27, 1999·42 cites·12 claims
- 1563US5611063AMethod for executing speculative load instructions in high-performance processorsIBM·Filed 1996·Granted Mar 11, 1997·44 cites·11 claims
- 1662US5913054AMethod and system for processing a multiple-register instruction that permit multiple data words to be written in a single processor cycleIBM·Filed 1996·Granted Jun 15, 1999·45 cites·8 claims
- 1761US7376686B2Apparatus and method for generating packed sum of absolute differencesVIA TECH INC·Filed 2004·Granted May 20, 2008·6 cites·6 claims
- 1861US5892699AMethod and apparatus for optimizing dependent operand flow within a multiplier using recoding logicINTEGRATED DEVICE TECH·Filed 1997·Granted Apr 6, 1999·40 cites·33 claims
- 1961US5694565AMethod and device for early deallocation of resources during load/store multiple operations to allow simultaneous dispatch/execution of subsequent instructionsIBM·Filed 1995·Granted Dec 2, 1997·34 cites·4 claims
- 2059US5867684AMethod and processor that permit concurrent execution of a store multiple instruction and a dependent instructionIBM·Filed 1997·Granted Feb 2, 1999·30 cites·2 claims
- 2154US5619408AMethod and system for recoding noneffective instructions within a data processing systemIBM·Filed 1995·Granted Apr 8, 1997·24 cites·11 claims
- 2252US10514920B2Dynamically updating hardware prefetch trait to exclusive or shared at program detectionVIA TECH INC·Filed 2015·Granted Dec 24, 2019·0 cites·21 claims
- 2350US9891916B2Dynamically updating hardware prefetch trait to exclusive or shared in multi-memory access agent systemVIA TECH INC·Filed 2015·Granted Feb 13, 2018·0 cites·23 claims
- 2450US2011010506A1Data prefetcher with multi-level table for predicting stride patternsVIA TECH INC·Filed 2009·Application pending·0 cites
- 2548US5765191AMethod for implementing a four-way least recently used (LRU) mechanism in high-performanceIBM·Filed 1996·Granted Jun 9, 1998·20 cites·8 claims
- 2646US8364906B2Avoiding memory access latency by returning hit-modified when holding non-modified dataVIA TECH INC·Filed 2010·Granted Jan 29, 2013·0 cites·22 claims
- 2745US6339823B1Method and apparatus for selective writing of incoherent MMX registersIP FIRST LLC·Filed 1999·Granted Jan 15, 2002·17 cites·21 claims
- 2845US5715420AMethod and system for efficient memory management in a data processing system utilizing a dual mode translation lookaside bufferIBM·Filed 1995·Granted Feb 3, 1998·20 cites·15 claims
- 2943US6134573AApparatus and method for absolute floating point register addressingIP FIRST LLC·Filed 1998·Granted Oct 17, 2000·14 cites·25 claims
- 3043US6014736AApparatus and method for improved floating point exchangeIP FIRST LLC·Filed 1998·Granted Jan 11, 2000·15 cites·24 claims
- 3142US6385716B1Method and apparatus for tracking coherence of dual floating point and MMX register filesIP FIRST LLC·Filed 1999·Granted May 7, 2002·13 cites·21 claims
- 3239US5754811AInstruction dispatch queue for improved instruction cache to queue timingFiled 1996·Granted May 19, 1998·11 cites·18 claims
- 3336US6412065B1Status register associated with MMX register file for tracking writesIP FIRST LLC·Filed 1999·Granted Jun 25, 2002·8 cites·16 claims
- 3436US5717587AMethod and system for recording noneffective instructions within a data processing systemIBM·Filed 1996·Granted Feb 10, 1998·7 cites·11 claims
- 3534US5758141AMethod and system for selective support of non-architected instructions within a superscaler processor system utilizing a special access bit within a machine state registerIBM·Filed 1995·Granted May 26, 1998·7 cites·8 claims
- 3633US5850563AProcessor and method for out-of-order completion of floating-point operations during load/store multiple operationsIBM·Filed 1995·Granted Dec 15, 1998·5 cites·4 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →