Inventor · disambiguated record
Albert Ma
Also filed as: MA ALBERT
12 granted patents·20 citations·filing 2014–2024
85Inventor score
Top patents by PatentIndex Score
12 records- 0191US12032488B1Circuit and method for translation lookaside buffer (TLB) implementationMARVELL ASIA PTE LTD·Filed 2022·Granted Jul 9, 2024·4 cites·32 claims
- 0291US11416405B1System and method for mapping memory addresses to locations in set-associative cachesMARVELL ASIA PTE LTD·Filed 2021·Granted Aug 16, 2022·4 cites·25 claims
- 0386US11960727B1System and method for large memory transaction (LMT) storesMARVELL ASIA PTE LTD·Filed 2022·Granted Apr 16, 2024·1 cites·35 claims
- 0484US9405702B2Caching TLB translations using a unified page table walker cacheCAVIUM INC·Filed 2014·Granted Aug 2, 2016·9 cites·24 claims
- 0575US12282658B1System and method for large memory transaction (LMT) storesMARVELL ASIA PTE LTD·Filed 2024·Granted Apr 22, 2025·0 cites·35 claims
- 0670US10303514B2Sharing resources in a multi-context computing systemCAVIUM LLC·Filed 2015·Granted May 28, 2019·2 cites·21 claims
- 0767US11620225B1System and method for mapping memory addresses to locations in set-associative cachesMARVELL ASIA PTE LTD·Filed 2022·Granted Apr 4, 2023·0 cites·25 claims
- 0854US9910776B2Instruction ordering for in-progress operationsCAVIUM INC·Filed 2014·Granted Mar 6, 2018·0 cites·34 claims
- 0953US10339054B2Instruction ordering for in-progress operationsCAVIUM LLC·Filed 2018·Granted Jul 2, 2019·0 cites·32 claims
- 1045US11474953B2Configuration cache for the ARM SMMUv3MARVELL ASIA PTE LTD·Filed 2018·Granted Oct 18, 2022·0 cites·21 claims
- 1144US9678717B2Distributing resource requests in a computing systemCAVIUM INC·Filed 2015·Granted Jun 13, 2017·0 cites·19 claims
- 1243US10078601B2Approach for interfacing a pipeline with two or more interfaces in a processorCAVIUM INC·Filed 2015·Granted Sep 18, 2018·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →