Inventor · disambiguated record
Alvan W. Ng
Also filed as: NG ALVAN · NG ALVAN W · NG ALVAN WING
23 granted patents·3 pending applications·139 citations·filing 1985–2021
94Inventor score
Top patents by PatentIndex Score
26 records- 0188US7500035B2Livelock resolution methodIBM·Filed 2006·Granted Mar 3, 2009·16 cites·20 claims
- 0283US8370783B2Systems and methods for probabilistic interconnect planningTOSHIBA KK·Filed 2007·Granted Feb 5, 2013·14 cites·15 claims
- 0383US8131980B2Structure for dynamic livelock resolution with variable delay memory access queueHALL RONALD·Filed 2008·Granted Mar 6, 2012·15 cites·17 claims
- 0482US8516412B2Soft hierarchy-based physical synthesis for large-scale, high-performance circuitsCHO MINSIK·Filed 2011·Granted Aug 20, 2013·8 cites·23 claims
- 0580US8225045B2Lateral cache-to-cache cast-inGUTHRIE GUY L·Filed 2008·Granted Jul 17, 2012·10 cites·23 claims
- 0671US8949540B2Lateral castout (LCO) of victim cache line in data-invalid stateGUTHRIE GUY L·Filed 2009·Granted Feb 3, 2015·5 cites·20 claims
- 0770US7519780B2System and method for reducing store latency in symmetrical multiprocessor systemsIBM·Filed 2006·Granted Apr 14, 2009·5 cites·35 claims
- 0869US4739473AComputer memory apparatusHONEYWELL INF SYSTEMS·Filed 1985·Granted Apr 19, 1988·27 cites·20 claims
- 0967US7681158B2Delay budget allocation with path trimmingTOSHIBA KK·Filed 2007·Granted Mar 16, 2010·4 cites·16 claims
- 1065US8327073B2Empirically based dynamic control of acceptance of victim cache lateral castoutsGUTHRIE GUY L·Filed 2009·Granted Dec 4, 2012·3 cites·27 claims
- 1165US8171448B2Structure for a livelock resolution circuitJOHNS CHARLES R·Filed 2008·Granted May 1, 2012·3 cites·18 claims
- 1264US7831812B2Method and apparatus for operating an age queue for memory request operations in a processor of an information handling systemIBM·Filed 2007·Granted Nov 9, 2010·3 cites·20 claims
- 1363US6751704B2Dual-L2 processor subsystem architecture for networking systemIBM·Filed 2000·Granted Jun 15, 2004·9 cites·15 claims
- 1462US8499124B2Handling castout cache lines in a victim cacheGUTHRIE GUY L·Filed 2008·Granted Jul 30, 2013·2 cites·11 claims
- 1557US7356713B2Method and apparatus for managing the power consumption of a data processing systemIBM·Filed 2003·Granted Apr 8, 2008·4 cites·18 claims
- 1657US6779162B2Method of analyzing and filtering timing runs using common timing characteristicsIBM·Filed 2002·Granted Aug 17, 2004·5 cites·16 claims
- 1755US7861022B2Livelock resolutionIBM·Filed 2009·Granted Dec 28, 2010·0 cites·20 claims
- 1853US10599804B1Pin cloning and subway creation on automatically generated design physical hierarchyIBM·Filed 2018·Granted Mar 24, 2020·0 cites·20 claims
- 1953US7721123B2Method and apparatus for managing the power consumption of a data processing systemIBM·Filed 2008·Granted May 18, 2010·0 cites·19 claims
- 2047US12050852B2Signal pre-routing in an integrated circuit designIBM·Filed 2021·Granted Jul 30, 2024·0 cites·20 claims
- 2145US12204832B2Logical clock connection in an integrated circuit designIBM·Filed 2021·Granted Jan 21, 2025·0 cites·22 claims
- 2245US2009064068A1Method and Apparatus for Evaluating the Timing Effects of Logic Block Location Changes in Integrated Circuit DesignIBM·Filed 2007·Application pending·0 cites
- 2343US2008065873A1Dynamic livelock resolution with variable delay memory access queueHALL RONALD·Filed 2006·Application pending·0 cites
- 2442US7171445B2Fixed snoop response time for source-clocked multiprocessor bussesIBM·Filed 2002·Granted Jan 30, 2007·0 cites·20 claims
- 2541US2003101297A1Dynamic request pacing in switch systemsIBM·Filed 2001·Application pending·0 cites
- 2637US4761730AComputer memory apparatusHONEYWELL BULL·Filed 1985·Granted Aug 2, 1988·6 cites·21 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →