Signal pre-routing in an integrated circuit design

Abstract

Based on a directive in a control file, a processor pre-routes, within a hierarchical integrated circuit design, a signal through one or more levels of design hierarchy between a signal source at a higher level of the design hierarchy and an entity instance at a lower level of the design hierarchy. The processor processes entity instances in the design hierarchy in a bottom-up manner to insert technology-specific structures into the hierarchical integrated circuit design. During the processing, the processor inserts into a particular entity instance of the design hierarchy a technology-specific structure and connects the technology-specific structure to the signal pre-routed to the particular entity instance by the pre-routing.

What is claimed is: 
     
       1. A method of simulating operation of an integrated circuit design in a data processing system including a processor and data storage, the method comprising:
 the processor of the data processing system constructing, within the data storage, a hierarchical integrated circuit design for an integrated circuit containing millions of transistors through execution of one or more electronic design automation (EDA) tools, wherein the hierarchical integrated circuit design includes a design hierarchy including a plurality of entity instances organized hierarchically in a plurality of levels including a lower level, one or more intermediate levels, and a higher level, and wherein the constructing includes:
 the processor pre-routing, within the hierarchical integrated circuit design, a signal through the one or more intermediate levels of the design hierarchy between a particular signal sourced at the higher level of the design hierarchy and a particular entity instance among the plurality of entity instances at the lower level of the design hierarchy, wherein the pre-routing includes pre-routing the particular signal based on a directive in a control file, said directive specifying the particular signal and the particular entity instance; 
 the processor performing default routing of a plurality of signals other than the particular signal in the hierarchical integrated circuit design; 
 after the pre-routing, the processor processing entity instances in the design hierarchy in a bottom-up manner to insert technology-specific structures into the hierarchical integrated circuit design, wherein the processing includes the processor inserting into the particular entity instance of the design hierarchy a technology-specific structure and connecting the technology-specific structure to the particular signal pre-routed to the particular entity instance by the pre-routing, such that routing of the particular signal to the technology-specific structure is determined by the pre-routing rather than the default routing; and 
 
 the processor performing logic synthesis on the hierarchical integrated circuit design, compiling the hierarchical integrated circuit design to obtain a technology-elaborated simulation model, and simulating operation of the hierarchical integrated circuit design utilizing the technology-elaborated simulation model. 
 
     
     
       2. The method of  claim 1 , wherein the pre-routing includes forming a port for the particular signal on the particular entity instance. 
     
     
       3. The method of  claim 2 , wherein the pre-routing includes placing a temporary anchor point for the particular signal within the particular entity instance. 
     
     
       4. The method of  claim 3 , wherein the pre-routing includes cloning, at the higher level of the design hierarchy, multiple copies of the temporary anchor point connected to the particular signal and specifying a respective one of a plurality of different signal routes for each of the temporary anchor points through one or more levels of the design hierarchy. 
     
     
       5. The method of  claim 1 , wherein:
 the particular entity instance is a first entity instance; and 
 the pre-routing includes establishing an input port and an output port for the particular signal on a second entity instance at the same lower level of the design hierarchy as the first entity instance. 
 
     
     
       6. The method of  claim 5 , wherein:
 the second entity instance is an instance of a given design entity; 
 the design hierarchy includes a third entity instance that is an instance of the given design entity; and 
 the pre-routing includes modifying the design hierarchy by making the second entity instance an instance of another design entity different than the given design entity. 
 
     
     
       7. The method of  claim 1 , wherein:
 the technology-specific structure includes a storage element configurable to function in a scan chain; and 
 the particular signal is a scan chain signal. 
 
     
     
       8. A program product, comprising:
 a storage device; and 
 program code stored within the storage device and executable by a processor to cause the processor to simulate operation of an integrated circuit design by performing:
 constructing, within data storage, a hierarchical integrated circuit design for an integrated circuit containing millions of transistors through execution of one or more electronic design automation (EDA) tools, wherein the hierarchical integrated circuit design includes a design hierarchy including a plurality of entity instances organized hierarchically in a plurality of levels including a lower level, one or more intermediate levels, and a higher level, and wherein the constructing includes:
 pre-routing, within the hierarchical integrated circuit design, a signal through the one or more intermediate levels of the design hierarchy between a signal sourced at the higher level of the design hierarchy and a particular entity instance among the plurality of entity instances at the lower level of the design hierarchy, wherein the pre-routing includes pre-routing the particular signal based on a directive in a control file, said directive specifying the particular signal and the particular entity instance; 
 performing default routing of a plurality of signals other than the particular signal in the hierarchical integrated circuit design; 
 after the pre-routing, processing entity instances in the design hierarchy in a bottom-up manner to insert technology-specific structures into the hierarchical integrated circuit design, wherein the processing includes inserting into the particular entity instance of the design hierarchy a technology-specific structure and connecting the technology-specific structure to the particular signal pre-routed to the particular entity instance by the pre-routing, such that routing of the particular signal to the technology-specific structure is determined by the pre-routing rather than the default routing; and 
 
 performing logic synthesis on the hierarchical integrated circuit design, compiling the hierarchical integrated circuit design to obtain a technology-elaborated simulation model, and simulating operation of the hierarchical integrated circuit design utilizing the technology- elaborated simulation model. 
 
 
     
     
       9. The program product of  claim 8 , wherein the pre-routing includes forming a port for the particular signal on the particular entity instance. 
     
     
       10. The program product of  claim 9 , wherein the pre-routing includes placing a temporary anchor point for the particular signal within the particular entity instance. 
     
     
       11. The program product of  claim 10 , wherein the pre-routing includes cloning, at the higher level of the design hierarchy, multiple copies of the temporary anchor point connected to the particular signal and specifying a respective one of a plurality of different signal routes for each of the temporary anchor points through one or more levels of the design hierarchy. 
     
     
       12. The program product of  claim 8 , wherein:
 the particular entity instance is a first entity instance; and 
 the pre-routing includes establishing an input port and an output port for the particular signal on a second entity instance at the same lower level of the design hierarchy as the first entity instance. 
 
     
     
       13. The program product of  claim 12 , wherein:
 the second entity instance is an instance of a given design entity; 
 the design hierarchy includes a third entity instance that is an instance of the given design entity; and 
 the pre-routing includes modifying the design hierarchy by making the second entity instance an instance of another design entity different than the given design entity. 
 
     
     
       14. The program product of  claim 8 , wherein:
 the technology-specific structure includes a storage element configurable to function in a scan chain; and 
 the particular signal is a scan chain signal. 
 
     
     
       15. A data processing system, comprising:
 a processor; and 
 data storage coupled to the processor, wherein the data storage includes program code executable by the processor to cause the processor to simulate operation of an integrated circuit design by performing:
 constructing, within data storage, a hierarchical integrated circuit design for an integrated circuit containing millions of transistors through execution of one or more electronic design automation (EDA) tools, wherein the hierarchical integrated circuit design includes a design hierarchy including a plurality of entity instances organized hierarchically in a plurality of levels including a lower level, one or more intermediate levels, and a higher level, and wherein the constructing includes:
 pre-routing, within the hierarchical integrated circuit design, a signal through the one or more intermediate levels of the design hierarchy between a signal sourced at the higher level of the design hierarchy and a particular entity instance among the plurality of entity instances at the lower level of the design hierarchy, wherein the pre-routing includes pre-routing the particular signal based on a directive in a control file, said directive specifying the particular signal and the particular entity instance; 
 performing default routing of a plurality of signals other than the particular signal in the hierarchical integrated circuit design; 
 after the pre-routing, processing entity instances in the design hierarchy in a bottom-up manner to insert technology-specific structures into the hierarchical integrated circuit design, wherein the processing includes inserting into the particular entity instance of the design hierarchy a technology-specific structure and connecting the technology-specific structure to the particular signal pre-routed to the particular entity instance by the pre-routing, such that routing of the particular signal to the technology-specific structure is determined by the pre-routing rather than the default routing; and 
 
 performing logic synthesis on the hierarchical integrated circuit design, compiling the hierarchical integrated circuit design to obtain a technology-elaborated simulation model, and simulating operation of the hierarchical integrated circuit design utilizing the technology-elaborated simulation model. 
 
 
     
     
       16. The data processing system of  claim 15 , wherein the pre-routing includes forming a port for the particular signal on the particular entity instance. 
     
     
       17. The data processing system of  claim 16 , wherein the pre-routing includes placing a temporary anchor point for the particular signal within the particular entity instance. 
     
     
       18. The data processing system of  claim 17 , wherein the pre-routing includes cloning, at the higher level of the design hierarchy, multiple copies of the temporary anchor point connected to the particular signal and specifying a respective one of a plurality of different signal routes for each of the temporary anchor points through one or more levels of the design hierarchy. 
     
     
       19. The data processing system of  claim 15 , wherein:
 the particular entity instance is a first entity instance; and 
 the pre-routing includes establishing an input port and an output port for the particular signal on a second entity instance at the same lower level of the design hierarchy as the first entity instance. 
 
     
     
       20. The data processing system of  claim 19 , wherein:
 the second entity instance is an instance of a given design entity; 
 the design hierarchy includes a third entity instance that is an instance of the given design entity; and 
 the pre-routing includes modifying the design hierarchy by making the second entity instance an instance of another design entity different than the given design entity.