Inventor · disambiguated record
Albin Pierrick Tonnerre
Also filed as: TONNERRE Albin Pierrick
26 granted patents·3 pending applications·57 citations·filing 2016–2024
92Inventor score
Technology areasG06F
Files withADVANCED RISC MACH LTD29
Top patents by PatentIndex Score
29 records- 0197US10394716B1Apparatus and method for controlling allocation of data into a cache storageADVANCED RISC MACH LTD·Filed 2018·Granted Aug 27, 2019·41 cites·19 claims
- 0287US11221951B1Skipping tag check for tag-checked load operationADVANCED RISC MACH LTD·Filed 2020·Granted Jan 11, 2022·9 cites·18 claims
- 0381US12423233B2Order enforcement for delegable memory accessesADVANCED RISC MACH LTD·Filed 2023·Granted Sep 23, 2025·1 cites·20 claims
- 0478US11340901B2Apparatus and method for controlling allocation of instructions into an instruction cache storageADVANCED RISC MACH LTD·Filed 2019·Granted May 24, 2022·2 cites·13 claims
- 0573US10635445B2Handling modifications to permitted program counter ranges in a data processing apparatusADVANCED RISC MACH LTD·Filed 2018·Granted Apr 28, 2020·2 cites·15 claims
- 0669US10831499B2Apparatus and method for performing branch predictionADVANCED RISC MACH LTD·Filed 2018·Granted Nov 10, 2020·1 cites·17 claims
- 0768US11231932B2Transactional recovery storage for branch history and return addresses to partially or fully restore the return stack and branch history register on transaction abortsADVANCED RISC MACH LTD·Filed 2019·Granted Jan 25, 2022·1 cites·16 claims
- 0862US12436891B1Allocation of store buffer entriesADVANCED RISC MACH LTD·Filed 2024·Granted Oct 7, 2025·0 cites·15 claims
- 0962US12112169B2Register freeing latencyADVANCED RISC MACH LTD·Filed 2023·Granted Oct 8, 2024·0 cites·16 claims
- 1058US12260218B2Cracking instructions into a plurality of micro-operationsADVANCED RISC MACH LTD·Filed 2023·Granted Mar 25, 2025·0 cites·20 claims
- 1156US12182261B2Controlling use of data determined by a resolve-pending speculative operationADVANCED RISC MACH LTD·Filed 2019·Granted Dec 31, 2024·0 cites·19 claims
- 1254US12340220B2Register mapping to map architectural registers to corresponding physical registers based on a mode indicating a register lengthADVANCED RISC MACH LTD·Filed 2023·Granted Jun 24, 2025·0 cites·20 claims
- 1353US11526615B2Speculative side-channel hint instructionADVANCED RISC MACH LTD·Filed 2019·Granted Dec 13, 2022·0 cites·17 claims
- 1452US11803388B2Apparatus and method for predicting source operand values and optimized processing of instructionsADVANCED RISC MACH LTD·Filed 2019·Granted Oct 31, 2023·0 cites·20 claims
- 1552US11720494B1Cache eviction control for a private cache in an out-of-order data processing apparatusADVANCED RISC MACH LTD·Filed 2022·Granted Aug 8, 2023·0 cites·13 claims
- 1652US11397584B2Tracking speculative data cachingADVANCED RISC MACH LTD·Filed 2019·Granted Jul 26, 2022·0 cites·11 claims
- 1752US11392383B2Apparatus and method for prefetching data itemsADVANCED RISC MACH LTD·Filed 2019·Granted Jul 19, 2022·0 cites·13 claims
- 1852US11126714B2Encoding of input to storage circuitryADVANCED RISC MACH LTD·Filed 2018·Granted Sep 21, 2021·0 cites·29 claims
- 1950US11550620B2Task dispatchADVANCED RISC MACH LTD·Filed 2021·Granted Jan 10, 2023·0 cites·20 claims
- 2048US11263133B2Cache control in presence of speculative read operationsADVANCED RISC MACH LTD·Filed 2019·Granted Mar 1, 2022·0 cites·14 claims
- 2147US11157277B2Data processing apparatus with respective banked registers for exception levelsADVANCED RISC MACH LTD·Filed 2019·Granted Oct 26, 2021·0 cites·9 claims
- 2247US11132202B2Cache control circuitry and methodsADVANCED RISC MACH LTD·Filed 2019·Granted Sep 28, 2021·0 cites·12 claims
- 2345US10977044B2Executing branch instructions following a speculation barrier instructionADVANCED RISC MACH LTD·Filed 2019·Granted Apr 13, 2021·0 cites·14 claims
- 2445US2020410088A1Micro-instruction cache annotations to indicate speculative side-channel risk condition for read instructionsADVANCED RISC MACH LTD·Filed 2019·Application pending·0 cites
- 2544US10558462B2Apparatus and method for storing source operands for operationsADVANCED RISC MACH LTD·Filed 2018·Granted Feb 11, 2020·0 cites·18 claims
- 2644US2023244606A1Circuitry and methodADVANCED RISC MACH LTD·Filed 2022·Application pending·0 cites
- 2740US11709782B2Memory address translationADVANCED RISC MACH LTD·Filed 2021·Granted Jul 25, 2023·0 cites·17 claims
- 2838US11748101B2Handling of single-copy-atomic load/store instruction with a memory access request shared by micro-operationsADVANCED RISC MACH LTD·Filed 2021·Granted Sep 5, 2023·0 cites·15 claims
- 2935US2016350115A1Register renamingADVANCED RISC MACH LTD·Filed 2016·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →