Cache eviction control for a private cache in an out-of-order data processing apparatus

Abstract

Apparatuses and methods relating to controlling cache evictions are disclosed. Processing circuitry which execute instructions out-of-order is provided with a private cache into which blocks of data are copied from a shared storage location to which the processing circuitry shares access. The processing circuitry also has a read-after-read buffer, into which an entry is allocated when out-of-order execution of a load instruction occurs comprising an address accessed by the load instruction. The address remains as a valid entry in the read-after-read buffer until the load instruction is committed. Eviction of an eviction candidate block of data from the private cache to the shared storage location is controlled in dependence on whether the eviction candidate block of data has a corresponding valid entry in the read-after-read buffer.

We claim: 
     
       1. Apparatus comprising:
 processing circuitry configured to execute instructions out-of-order with respect to a programmed sequence of the instructions; 
 a private cache associated with the processing circuitry and configured to store copies of blocks of data comprising data which the instructions subject to data processing operations, wherein a block of data is copied into the private cache from a shared storage location to which the processing circuitry shares access; 
 a read-after-read buffer, wherein out-of-order execution of a load instruction by the processing circuitry is configured to cause allocation of an entry in the read-after-read buffer comprising an address accessed by the load instruction, wherein the address remains as a valid entry in the read-after-read buffer until the load instruction is committed; and 
 cache content control circuitry is configured to control an eviction of an eviction candidate block of data from the private cache to the shared storage location in dependence on whether the eviction candidate block of data has a corresponding valid entry in the read-after-read buffer. 
 
     
     
       2. The apparatus as claimed in  claim 1 , wherein the private cache associated with the processing circuitry forms part of a hierarchy of cache levels,
 and the cache content control circuitry is configured to control the eviction such that when the candidate block of data is evicted from a first level of the hierarchy the eviction candidate block of data either is allocated into a second level of the hierarchy or is evicted to the shared storage location in dependence on whether the eviction candidate block of data has the corresponding valid entry in the read-after-read buffer. 
 
     
     
       3. The apparatus as claimed in  claim 1 , wherein the shared storage location to which the processing circuitry shares access comprises a shared cache to which further processing circuitry other than the processing circuitry also has access. 
     
     
       4. The apparatus as claimed in  claim 1 , wherein the shared storage location to which the processing circuitry shares access comprises a memory to which further processing circuitry other than the processing circuitry also has access. 
     
     
       5. The apparatus as claimed in  claim 1 , wherein the data which the instructions subject to data processing operations is stored in memory in association with a transient marker, wherein the transient marker is set for data for which a caching benefit is expected to be short-lived,
 and wherein each block of data in the private cache has a corresponding transient marker held in association therewith, 
 and the eviction candidate block of data for which the cache content control circuitry is configured to control the eviction is a block of data for which the corresponding transient marker held in association therewith is set. 
 
     
     
       6. The apparatus as claimed in  claim 1 , wherein the read-after-read buffer is configured to monitor evictions from the private cache to the shared storage location,
 wherein, when a monitored eviction from the private cache to the shared storage location concerns a monitored eviction block of data which has a corresponding valid entry in the read-after-read buffer, the read-after-read buffer is configured to store a hazard indicator in association with the entry, 
 and the read-after-read buffer is responsive to out-of-order execution of an older load instruction to determine a hazard condition to be true when an entry for a younger load instruction has the hazard indicator, and when the hazard condition is true, to signal the data hazard condition to the processing circuitry and to cause a portion of the programmed sequence of the instructions comprising the older load instruction and the younger load instruction to be re-executed. 
 
     
     
       7. A method of data processing comprising:
 executing instructions in processing circuitry out-of-order with respect to a programmed sequence of the instructions; 
 storing copies of blocks of data comprising data which the instructions subject to data processing operations in a private cache associated with the processing circuitry, wherein a block of data is copied into the private cache from a shared storage location to which the processing circuitry shares access; 
 allocating an entry into a read-after-read buffer in response to out-of-order execution of a load instruction, the entry comprising an address accessed by the load instruction, wherein the address remains as a valid entry in the read-after-read buffer until the load instruction is committed; and 
 controlling an eviction of an eviction candidate block of data from the private cache to the shared storage location in dependence on whether the eviction candidate block of data has a corresponding valid entry in the read-after-read buffer. 
 
     
     
       8. The method as claimed in  claim 7 , wherein the private cache associated with the processing circuitry forms part of a hierarchy of cache levels,
 and controlling the eviction is performed such that, when the candidate block of data is evicted from a first level of the hierarchy, the eviction candidate block of data either is allocated into a second level of the hierarchy or is evicted to the shared storage location in dependence on whether the eviction candidate block of data has the corresponding valid entry in the read-after-read buffer. 
 
     
     
       9. The method as claimed in  claim 7 , wherein the shared storage location to which the processing circuitry shares access comprises a shared cache to which further processing circuitry other than the processing circuitry also has access. 
     
     
       10. The method as claimed in  claim 7 , wherein the shared storage location to which the processing circuitry shares access comprises a memory to which further processing circuitry other than the processing circuitry also has access. 
     
     
       11. The method as claimed in  claim 7 , wherein the data which the instructions subject to data processing operations is stored in memory in association with a transient marker, wherein the transient marker is set for data for which a caching benefit is expected to be short-lived,
 and wherein each block of data in the private cache has a corresponding transient marker held in association therewith, 
 and the eviction candidate block of data for which the cache content control circuitry is configured to control the eviction is a block of data for which the corresponding transient marker held in association therewith is set. 
 
     
     
       12. The method as claimed in  claim 7 , further comprising:
 monitoring evictions from the private cache to the shared storage location; 
 in response to a monitored eviction from the private cache to the shared storage location concerning a monitored eviction block of data which has a corresponding valid entry in the read-after-read buffer, storing a hazard indicator in association with the entry in the read-after-read buffer; 
 in response to out-of-order execution of an older load instruction, determining a hazard condition to be true when an entry for a younger load instruction has the hazard indicator; 
 and when the hazard condition is true, signalling the data hazard condition to the processing circuitry and causing a portion of the programmed sequence of the instructions comprising the older load instruction and the younger load instruction to be re-executed. 
 
     
     
       13. Apparatus comprising:
 means for executing instructions out-of-order with respect to a programmed sequence of the instructions; 
 means for storing copies of blocks of data comprising data which the instructions subject to data processing operations in a private cache associated with the means for executing instructions, wherein a block of data is copied into the private cache from a shared storage location to which the means for executing instructions shares access; 
 means for allocating an entry into a read-after-read buffer in response to out-of-order execution of a load instruction, the entry comprising an address accessed by the load instruction, wherein the address remains as a valid entry in the read-after-read buffer until the load instruction is committed; and 
 means for controlling an eviction of an eviction candidate block of data from the private cache to the shared storage location in dependence on whether the eviction candidate block of data has a corresponding valid entry in the read-after-read buffer.