Inventor · disambiguated record
Albert M. Young
Also filed as: YOUNG ALBERT · YOUNG ALBERT M · YOUNG ALBERT MIEBACH
44 granted patents·17 pending applications·489 citations·filing 1999–2023
97Inventor score
Top patents by PatentIndex Score
61 records- 0197US8546188B2Bow-balanced 3D chip stackingLIU FEI·Filed 2010·Granted Oct 1, 2013·82 cites·24 claims
- 0296US6396298B1Active feedback pulsed measurement methodAEROSPACE CORP·Filed 2000·Granted May 28, 2002·132 cites·20 claims
- 0394US11145550B2Dummy fin template to form a self-aligned metal contact for output of vertical transport field effect transistorIBM·Filed 2020·Granted Oct 12, 2021·3 cites·15 claims
- 0493US12268031B2Backside power rails and power distribution network for density scalingIBM·Filed 2021·Granted Apr 1, 2025·2 cites·12 claims
- 0589US7913202B2Wafer level I/O test, repair and/or customization enabled by I/O layerIBM·Filed 2007·Granted Mar 22, 2011·22 cites·18 claims
- 0689US7521950B2Wafer level I/O test and repair enabled by I/O layerIBM·Filed 2005·Granted Apr 21, 2009·21 cites·5 claims
- 0786US8492869B23D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layerFAROOQ MUKTA G·Filed 2012·Granted Jul 23, 2013·5 cites·20 claims
- 0886US6177836B1Feed forward linearized traveling wave tubeAEROSPACE CORP·Filed 1999·Granted Jan 23, 2001·64 cites·16 claims
- 0986US6127899AHigh frequency anharmonic oscillator for the generation of broadband deterministic noiseAEROSPACE CORP·Filed 1999·Granted Oct 3, 2000·62 cites·20 claims
- 1085US7683478B2Hermetic seal and reliable bonding structures for 3D applicationsIBM·Filed 2008·Granted Mar 23, 2010·9 cites·3 claims
- 1184US8298914B23D integrated circuit device fabrication using interface wafer as permanent carrierFAROOQ MUKTA G·Filed 2008·Granted Oct 30, 2012·7 cites·10 claims
- 1284US7256649B2Multiple signal intermodulation reduction systemAEROSPACE CORP·Filed 2005·Granted Aug 14, 2007·19 cites·19 claims
- 1376US7847597B1Precision frequency change detectorAEROSPACE CORP·Filed 2009·Granted Dec 7, 2010·10 cites·14 claims
- 1476US7545667B2Programmable via structure for three dimensional integration technologyIBM·Filed 2006·Granted Jun 9, 2009·6 cites·3 claims
- 1576US7528056B2Low-cost strained SOI substrate for high-performance CMOS technologyIBM·Filed 2007·Granted May 5, 2009·5 cites·16 claims
- 1675US11956939B2Static random access memory using vertical transport field effect transistorsIBM·Filed 2023·Granted Apr 9, 2024·0 cites·20 claims
- 1775US8664081B2Method for fabricating 3D integrated circuit device using interface wafer as permanent carrierFAROOQ MUKTA G·Filed 2012·Granted Mar 4, 2014·2 cites·20 claims
- 1871US7786596B2Hermetic seal and reliable bonding structures for 3D applicationsIBM·Filed 2008·Granted Aug 31, 2010·3 cites·5 claims
- 1971US7732798B2Programmable via structure for three dimensional integration technologyIBM·Filed 2008·Granted Jun 8, 2010·4 cites·9 claims
- 2069US8399336B2Method for fabricating a 3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layerFAROOQ MUKTA G·Filed 2008·Granted Mar 19, 2013·2 cites·20 claims
- 2169US7737003B2Method and structure for optimizing yield of 3-D chip manufactureIBM·Filed 2005·Granted Jun 15, 2010·4 cites·18 claims
- 2269US7129783B2Hybrid active combiner and circulatorAEROSPACE CORP·Filed 2004·Granted Oct 31, 2006·17 cites·7 claims
- 2368US7652278B2Programmable via structure and method of fabricating sameIBM·Filed 2006·Granted Jan 26, 2010·3 cites·20 claims
- 2467US11678475B2Static random access memory using vertical transport field effect transistorsIBM·Filed 2021·Granted Jun 13, 2023·0 cites·20 claims
- 2566US12278184B2Vertically-stacked field effect transistor cellIBM·Filed 2022·Granted Apr 15, 2025·0 cites·18 claims
- 2666US11710666B2Dummy fin template to form a self-aligned metal contact for output of vertical transport field effect transistorIBM·Filed 2021·Granted Jul 25, 2023·0 cites·15 claims
- 2764US8174841B2Adaptive interconnect structureCHANG LELAND·Filed 2009·Granted May 8, 2012·2 cites·25 claims
- 2863US12484265B2Subtractive source drain contact for stacked devicesIBM·Filed 2022·Granted Nov 25, 2025·0 cites·20 claims
- 2963US12477819B2Stacked FET with extremely small cell heightIBM·Filed 2022·Granted Nov 18, 2025·0 cites·20 claims
- 3063US8828800B2Method of forming adaptive interconnect structure having programmable contactsCHANG LELAND·Filed 2012·Granted Sep 9, 2014·1 cites·20 claims
- 3162US12490465B2Stacked field effect transistorIBM·Filed 2022·Granted Dec 2, 2025·0 cites·20 claims
- 3262US12424591B2Method and structure of forming independent contact for staggered CFETIBM·Filed 2022·Granted Sep 23, 2025·0 cites·20 claims
- 3361US12322652B2Local interconnect for cross couplingIBM·Filed 2022·Granted Jun 3, 2025·0 cites·20 claims
- 3461US7999377B2Method and structure for optimizing yield of 3-D chip manufactureIBM·Filed 2008·Granted Aug 16, 2011·2 cites·7 claims
- 3560US12310072B2Middle of line structure with stacked devicesIBM·Filed 2021·Granted May 20, 2025·0 cites·14 claims
- 3659US12446320B2Bottom contact with self-aligned spacer for stacked semiconductor devicesIBM·Filed 2022·Granted Oct 14, 2025·0 cites·16 claims
- 3758US12268026B2High aspect ratio contact structure with multiple metal stacksIBM·Filed 2022·Granted Apr 1, 2025·0 cites·20 claims
- 3858US11915966B2Backside power rail integrationIBM·Filed 2021·Granted Feb 27, 2024·0 cites·7 claims
- 3958US9755506B2Efficient voltage conversionIBM·Filed 2014·Granted Sep 5, 2017·0 cites·14 claims
- 4058US2024164089A1Backside programmable memoryIBM·Filed 2022·Application pending·0 cites
- 4157US12136655B2Backside electrical contacts to buried power railsIBM·Filed 2021·Granted Nov 5, 2024·0 cites·16 claims
- 4257US7888164B2Programmable via structure and method of fabricating sameIBM·Filed 2009·Granted Feb 15, 2011·0 cites·17 claims
- 4356US2024194601A1Power tap cell for front side power rail connection to bspdnIBM·Filed 2022·Application pending·0 cites
- 4456US2024162231A1Backside programmable gate arrayIBM·Filed 2022·Application pending·0 cites
- 4556US2024234306A9Self-aligned zero track skipIBM·Filed 2022·Application pending·0 cites
- 4655US8962448B2Computer readable medium encoded with a program for fabricating 3D integrated circuit device using interface wafer as permanent carrierFAROOQ MUKTA G·Filed 2012·Granted Feb 24, 2015·0 cites·20 claims
- 4754US2023402379A1Hybrid signal and power track for stacked transistorsIBM·Filed 2022·Application pending·0 cites
- 4854US2023420303A1Enhanced power and signal for stacked-fetsIBM·Filed 2022·Application pending·0 cites
- 4954US2023420367A1Contacts for stacked field effect transistorIBM·Filed 2022·Application pending·0 cites
- 5054US2023387007A1Interconnect through gate cut for stacked fet deviceIBM·Filed 2022·Application pending·0 cites
Showing the top 50 of 61 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Albert M. Young files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →