Inventor · disambiguated record
Amit Dhuria
Also filed as: DHURIA AMIT
12 granted patents·147 citations·filing 2013–2022
90Inventor score
Technology areasG06F
Files withCADENCE DESIGN SYSTEMS INC12
Top patents by PatentIndex Score
12 records- 0196US8788995B1System and method for guiding remedial transformations of a circuit design defined by physical implementation data to reduce needed physical corrections for detected timing violations in the circuit designCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Jul 22, 2014·55 cites·16 claims
- 0294US10990733B1Shared timing graph propagation for multi-mode multi-corner static timing analysisCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Apr 27, 2021·8 cites·20 claims
- 0394US8863052B1System and method for generating and using a structurally aware timing model for representative operation of a circuit designCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Oct 14, 2014·44 cites·18 claims
- 0489US11003821B1Deterministic loop breaking in multi-mode multi-corner static timing analysis of integrated circuitsCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted May 11, 2021·6 cites·20 claims
- 0588US10169501B1Timing context generation with multi-instance blocks for hierarchical analysisCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jan 1, 2019·7 cites·20 claims
- 0688US10037394B1Hierarchical timing analysis for multi-instance blocksCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jul 31, 2018·8 cites·20 claims
- 0785US9529962B1System and method for generating and using sibling nets model for shared delay calculation across multi-instantiated blocks in the circuit designCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Dec 27, 2016·6 cites·20 claims
- 0885US9405882B1High performance static timing analysis system and method for input/output interfacesCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Aug 2, 2016·6 cites·19 claims
- 0982US11144698B1Method, system, and product for an improved approach to placement and optimization in a physical design flowCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Oct 12, 2021·2 cites·20 claims
- 1079US10133842B1Methods, systems, and articles of manufacture for multi-mode, multi-corner physical optimization of electronic designsCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Nov 20, 2018·4 cites·22 claims
- 1168US11188696B1Method, system, and product for deferred merge based method for graph based analysis pessimism reductionCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Nov 30, 2021·1 cites·20 claims
- 1250US12475286B1System and method for comparing circuit design constraint setsCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Nov 18, 2025·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →