Inventor · disambiguated record
Annalisa Cappellani
Also filed as: CAPPELLANI ANNALISA
51 granted patents·5 pending applications·839 citations·filing 2001–2025
98Inventor score
Top patents by PatentIndex Score
56 records- 0198US9583491B2CMOS nanowire structureKIM SEIYON·Filed 2015·Granted Feb 28, 2017·28 cites·15 claims
- 0298US9224810B2CMOS nanowire structureKIM SEIYON·Filed 2011·Granted Dec 29, 2015·44 cites·23 claims
- 0398US9129829B2Silicon and silicon germanium nanowire structuresKUHN KELIN J·Filed 2014·Granted Sep 8, 2015·62 cites·13 claims
- 0498US8753942B2Silicon and silicon germanium nanowire structuresKUHN KELIN J·Filed 2010·Granted Jun 17, 2014·144 cites·30 claims
- 0598US7569443B2Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gateINTEL CORP·Filed 2005·Granted Aug 4, 2009·72 cites·9 claims
- 0697US8313999B2Multi-gate semiconductor device with self-aligned epitaxial source and drainCAPPELLANI ANNALISA·Filed 2009·Granted Nov 20, 2012·70 cites·14 claims
- 0797US7355281B2Method for making semiconductor device having a high-k gate dielectric layer and a metal gate electrodeINTEL CORP·Filed 2006·Granted Apr 8, 2008·47 cites·12 claims
- 0896US9472613B2Conversion of strain-inducing buffer to electrical insulatorINTEL CORP·Filed 2015·Granted Oct 18, 2016·13 cites·20 claims
- 0996US9461143B2Gate contact structure over active gate and method to fabricate samePETHE ABHIJIT JAYANT·Filed 2012·Granted Oct 4, 2016·62 cites·28 claims
- 1096US8735869B2Strained gate-all-around semiconductor devices formed on globally or locally isolated substratesCAPPELLANI ANNALISA·Filed 2012·Granted May 27, 2014·22 cites·18 claims
- 1196US7153784B2Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrodeINTEL CORP·Filed 2004·Granted Dec 26, 2006·86 cites·48 claims
- 1295US9224808B2Uniaxially strained nanowire structureCEA STEPHEN M·Filed 2011·Granted Dec 29, 2015·17 cites·43 claims
- 1394US9608059B2Semiconductor device with isolated body portionCAPPELLANI ANNALISA·Filed 2011·Granted Mar 28, 2017·18 cites·28 claims
- 1493US10074573B2CMOS nanowire structureINTEL CORP·Filed 2017·Granted Sep 11, 2018·8 cites·18 claims
- 1593US9595581B2Silicon and silicon germanium nanowire structuresINTEL CORP·Filed 2015·Granted Mar 14, 2017·7 cites·19 claims
- 1693US9564522B2Nanowire structures having non-discrete source and drain regionsCEA STEPHEN M·Filed 2015·Granted Feb 7, 2017·6 cites·9 claims
- 1793US9129827B2Conversion of strain-inducing buffer to electrical insulatorCAPPELLANI ANNALISA·Filed 2012·Granted Sep 8, 2015·12 cites·25 claims
- 1893US9087863B2Nanowire structures having non-discrete source and drain regionsCEA STEPHEN M·Filed 2011·Granted Jul 21, 2015·10 cites·17 claims
- 1992US10026829B2Semiconductor device with isolated body portionINTEL CORP·Filed 2017·Granted Jul 17, 2018·8 cites·25 claims
- 2091US9691843B2Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or compositionINTEL CORP·Filed 2016·Granted Jun 27, 2017·7 cites·11 claims
- 2190US9041106B2Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substratesCAPPELLANI ANNALISA·Filed 2012·Granted May 26, 2015·9 cites·24 claims
- 2289US8148786B2Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gateKAVALIEROS JACK·Filed 2009·Granted Apr 3, 2012·15 cites·5 claims
- 2389US2025185316A1Silicon and silicon germanium nanowire structuresSONY GROUP CORP·Filed 2024·Application pending·0 cites
- 2488US10192783B2Gate contact structure over active gate and method to fabricate sameINTEL CORP·Filed 2016·Granted Jan 29, 2019·4 cites·18 claims
- 2588US9583487B2Semiconductor device having metallic source and drain regionsGILES MARTIN D·Filed 2011·Granted Feb 28, 2017·10 cites·23 claims
- 2686US9905650B2Uniaxially strained nanowire structureINTEL CORP·Filed 2016·Granted Feb 27, 2018·3 cites·20 claims
- 2786US9559160B2Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or compositionCAPPELLANI ANNALISA·Filed 2011·Granted Jan 31, 2017·5 cites·15 claims
- 2885US10424580B2Semiconductor devices having modulated nanowire countsCAPPELLANI ANNALISA·Filed 2011·Granted Sep 24, 2019·6 cites·25 claims
- 2984US9484272B2Methods for fabricating strained gate-all-around semiconductor devices by fin oxidation using an undercut etch-stop layerCAPPELLANI ANNALISA·Filed 2014·Granted Nov 1, 2016·4 cites·6 claims
- 3084US7671471B2Method for making a semiconductor device having a high-k dielectric layer and a metal gate electrodeINTEL CORP·Filed 2008·Granted Mar 2, 2010·8 cites·18 claims
- 3183US12125916B2Nanowire structures having non-discrete source and drain regionsGOOGLE LLC·Filed 2022·Granted Oct 22, 2024·0 cites·7 claims
- 3282US9673302B2Conversion of strain-inducing buffer to electrical insulatorINTEL CORP·Filed 2016·Granted Jun 6, 2017·2 cites·20 claims
- 3382US2025233020A1Gate contact structure over active gate and method to fabricate sameINTEL CORP·Filed 2025·Application pending·0 cites
- 3481US9490320B2Uniaxially strained nanowire structureINTEL CORP·Filed 2015·Granted Nov 8, 2016·2 cites·16 claims
- 3579US10847631B2Gate-all-around (GAA) transistors with nanowires on an isolation pedestalINTEL CORP·Filed 2019·Granted Nov 24, 2020·1 cites·11 claims
- 3679US9472399B2Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substratesINTEL CORP·Filed 2015·Granted Oct 18, 2016·2 cites·8 claims
- 3777US9029221B2Semiconductor devices having three-dimensional bodies with modulated heightsCAPPELLANI ANNALISA·Filed 2011·Granted May 12, 2015·4 cites·26 claims
- 3876US12142634B2Silicon and silicon germanium nanowire structuresSONY GROUP CORP·Filed 2021·Granted Nov 12, 2024·0 cites·25 claims
- 3976US11004739B2Gate contact structure over active gate and method to fabricate sameINTEL CORP·Filed 2018·Granted May 11, 2021·1 cites·20 claims
- 4075US10229981B2Gate-all-around (GAA) transistor with stacked nanowires on locally isolated substrateINTEL CORP·Filed 2016·Granted Mar 12, 2019·1 cites·3 claims
- 4174US12278144B2Gate contact structure over active gate and method to fabricate sameINTEL CORP·Filed 2021·Granted Apr 15, 2025·0 cites·20 claims
- 4274US9425212B2Isolated and bulk semiconductor devices formed on a same bulk substrateCAPPELLANI ANNALISA·Filed 2012·Granted Aug 23, 2016·3 cites·14 claims
- 4374US8507948B2Junctionless accumulation-mode devices on prominent architectures, and methods of making sameCAPPELLANI ANNALISA·Filed 2010·Granted Aug 13, 2013·3 cites·17 claims
- 4473US10991799B2Silicon and silicon germanium nanowire structuresSONY CORP·Filed 2020·Granted Apr 27, 2021·0 cites·19 claims
- 4572US11552197B2Nanowire structures having non-discrete source and drain regionsGOOGLE LLC·Filed 2020·Granted Jan 10, 2023·0 cites·6 claims
- 4664US10636871B2Silicon and silicon germanium nanowire structuresINTEL CORP·Filed 2017·Granted Apr 28, 2020·0 cites·19 claims
- 4763US8853741B2Junctionless accumulation-mode devices on decoupled prominent architecturesINTEL CORP·Filed 2013·Granted Oct 7, 2014·1 cites·24 claims
- 4860US10580899B2Nanowire structures having non-discrete source and drain regionsINTEL CORP·Filed 2017·Granted Mar 3, 2020·0 cites·17 claims
- 4954US6835612B2Method for fabricating a MOSFET having a very small channel lengthINFINEON TECHNOLOGIES AG·Filed 2003·Granted Dec 28, 2004·7 cites·13 claims
- 5052US9978636B2Isolated and bulk semiconductor devices formed on a same bulk substrateINTEL CORP·Filed 2016·Granted May 22, 2018·0 cites·14 claims
Showing the top 50 of 56 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →