Inventor · disambiguated record
Andrew Cofler
Also filed as: COFLER ANDREW
24 granted patents·5 pending applications·508 citations·filing 1993–2024
96Inventor score
Top patents by PatentIndex Score
29 records- 0195US5596285AImpedance adaptation process and device for a transmitter and/or receiver, integrated circuit and transmission systemBULL SA·Filed 1994·Granted Jan 21, 1997·126 cites·22 claims
- 0287US6754856B2Memory access debug facilityST MICROELECTRONICS SA·Filed 2000·Granted Jun 22, 2004·58 cites·17 claims
- 0385US6959379B1Multiple execution of instruction loops within a processor without accessing program memoryST MICROELECTRONICS SA·Filed 2000·Granted Oct 25, 2005·44 cites·12 claims
- 0484US5614841AFrequency multiplier using XOR/NXOR gates which have equal propagation delaysBULL SA·Filed 1994·Granted Mar 25, 1997·43 cites·18 claims
- 0580US7281119B1Selective vertical and horizontal dependency resolution via split-bit propagation in a mixed-architecture system having superscalar and VLIW modesST MICROELECTRONICS SA·Filed 2000·Granted Oct 9, 2007·35 cites·20 claims
- 0676US6711668B1Prefetch unitST MICROELECTRONICS SA·Filed 2000·Granted Mar 23, 2004·24 cites·14 claims
- 0775US7496737B2High priority guard transfer for execution control of dependent guarded instructionsST MICROELECTRONICS SA·Filed 2005·Granted Feb 24, 2009·8 cites·23 claims
- 0875US6732276B1Guarded computer instruction executionST MICROELECTRONICS SA·Filed 2000·Granted May 4, 2004·23 cites·14 claims
- 0973US6807626B1Execution of a computer programST MICROELECTRONICS SA·Filed 2000·Granted Oct 19, 2004·20 cites·13 claims
- 1072US6725365B1Branching in a computer systemST MICROELECTRONICS SA·Filed 2000·Granted Apr 20, 2004·19 cites·21 claims
- 1172US5327031AVariable-delay circuitBULL SA·Filed 1993·Granted Jul 5, 1994·29 cites·11 claims
- 1269US6678818B1Decoding next instruction of different length without length mode indicator change upon length change instruction detectionST MICROELECTRONICS SA·Filed 2000·Granted Jan 13, 2004·15 cites·12 claims
- 1363US7111152B1Computer system that operates in VLIW and superscalar modes and has selectable dependency controlST MICROELECTRONICS SA·Filed 2000·Granted Sep 19, 2006·11 cites·13 claims
- 1462US7290089B2Executing cache instructions in an increased latency modeST MICROELECTRONICS SA·Filed 2002·Granted Oct 30, 2007·12 cites·18 claims
- 1562US6889313B1Selection of decoder output from two different length instruction decodersST MICROELECTRONICS SA·Filed 2000·Granted May 3, 2005·9 cites·18 claims
- 1661US7685470B2Method and device for debugging a program executed by a multitask processorST MICROELECTRONICS SA·Filed 2006·Granted Mar 23, 2010·2 cites·28 claims
- 1758US6854049B2Method of handling instructions within a processor with decoupled architecture, in particular a processor for digital signal processing, and corresponding processorST MICROELECTRONICS SA·Filed 2002·Granted Feb 8, 2005·6 cites·37 claims
- 1858US2025209033A1Communication via serializer/deserializerST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 1951US7013256B2Computer system with debug facilityST MICROELECTRONICS SA·Filed 2001·Granted Mar 14, 2006·3 cites·18 claims
- 2049US7240185B2Computer system with two debug watch modes for controlling execution of guarded instructions upon breakpoint detectionST MICROELECTRONICS SA·Filed 2000·Granted Jul 3, 2007·2 cites·18 claims
- 2149US6742131B1Instruction supply mechanismST MICROELECTRONICS SA·Filed 2000·Granted May 25, 2004·1 cites·21 claims
- 2248US7441109B2Computer system with a debug facility for a pipelined processor using predicated executionSGS THOMSON MICROELECTRONICS·Filed 2006·Granted Oct 21, 2008·0 cites·10 claims
- 2346US7486582B2Dynamic memory for a cellular terminalST MICROELECTRONICS SA·Filed 2006·Granted Feb 3, 2009·2 cites·11 claims
- 2445US7370182B2Method of handling branching instructions within a processor, in particular a processor for digital signal processing, and corresponding processorST MICROELECTRONICS SA·Filed 2002·Granted May 6, 2008·2 cites·29 claims
- 2545US2005010724A1Method of controlling a cache memory, and corresponding cache memory deviceST MICROELECTRONICS SA·Filed 2004·Application pending·0 cites
- 2643US2004158695A1Method and apparatus for handling transfer of guarded instructions in a computer systemFiled 2003·Application pending·0 cites
- 2741US2001007125A1Computer system with debug facilityFiled 2000·Application pending·0 cites
- 2839US2001025237A1Computer system with debug facilityFiled 2000·Application pending·0 cites
- 2937US5848109AApparatus and process for sampling a serial digital signalBULL SA·Filed 1995·Granted Dec 8, 1998·14 cites·44 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →