Inventor · disambiguated record
Anton J. Devilliers
Also filed as: DEVILLIERS ANTON · DEVILLIERS ANTON J
205 granted patents·26 pending applications·807 citations·filing 2008–2025
99Inventor score
Top patents by PatentIndex Score
231 records- 0199US11640118B2Method of pattern alignment for field stitchingTOKYO ELECTRON LTD·Filed 2021·Granted May 2, 2023·4 cites·19 claims
- 0298US10991626B2Method for controlling transistor delay of nanowire or nanosheet transistor devicesTOKYO ELECTRON LTD·Filed 2020·Granted Apr 27, 2021·6 cites·13 claims
- 0398US10734224B2Method and device for incorporating single diffusion break into nanochannel structures of FET devicesTOKYO ELECTRON LTD·Filed 2018·Granted Aug 4, 2020·20 cites·15 claims
- 0498US10586765B2Buried power railsTOKYO ELECTRON LTD·Filed 2018·Granted Mar 10, 2020·62 cites·20 claims
- 0598US10453850B2Three-dimensional semiconductor device including integrated circuit, transistors and transistor components and method of fabricationTOKYO ELECTRON LTD·Filed 2017·Granted Oct 22, 2019·23 cites·18 claims
- 0698US10388519B2Method and device for incorporating single diffusion break into nanochannel structures of FET devicesTOKYO ELECTRON LTD·Filed 2018·Granted Aug 20, 2019·23 cites·20 claims
- 0798US9837314B2Self-alignment of metal and via using selective depositionTOKYO ELECTRON LTD·Filed 2017·Granted Dec 5, 2017·27 cites·10 claims
- 0897US11630397B2Method for producing overlay results with absolute reference for semiconductor manufacturingTOKYO ELECTRON LTD·Filed 2021·Granted Apr 18, 2023·2 cites·20 claims
- 0997US11631671B23D complementary metal oxide semiconductor (CMOS) device and method of forming the sameTOKYO ELECTRON LTD·Filed 2020·Granted Apr 18, 2023·5 cites·23 claims
- 1097US11264274B2Reverse contact and silicide process for three-dimensional logic devicesTOKYO ELECTRON LTD·Filed 2020·Granted Mar 1, 2022·5 cites·20 claims
- 1197US10833078B2Semiconductor apparatus having stacked gates and method of manufacture thereofTOKYO ELECTRON LTD·Filed 2018·Granted Nov 10, 2020·34 cites·20 claims
- 1297US10573655B2Three-dimensional semiconductor device and method of fabricationTOKYO ELECTRON LTD·Filed 2018·Granted Feb 25, 2020·14 cites·12 claims
- 1397US9997598B2Three-dimensional semiconductor device and method of fabricationTOKYO ELECTRON LTD·Filed 2017·Granted Jun 12, 2018·26 cites·20 claims
- 1497US9645495B2Critical dimension control in photo-sensitized chemically-amplified resistTOKYO ELECTRON LTD·Filed 2015·Granted May 9, 2017·13 cites·16 claims
- 1596US10811265B2Location-specific tuning of stress to control bow to control overlay in semiconductor processingTOKYO ELECTRON LTD·Filed 2019·Granted Oct 20, 2020·10 cites·20 claims
- 1696US10770479B2Three-dimensional device and method of forming the sameTOKYO ELECTRON LTD·Filed 2019·Granted Sep 8, 2020·20 cites·20 claims
- 1796US10529830B2Extension region for a semiconductor deviceTOKYO ELECTRON LTD·Filed 2017·Granted Jan 7, 2020·16 cites·14 claims
- 1896US10032719B2Semiconductor device structuresMICRON TECHNOLOGY INC·Filed 2017·Granted Jul 24, 2018·16 cites·20 claims
- 1996US9818611B2Methods of forming etch masks for sub-resolution substrate patterningTOKYO ELECTRON LTD·Filed 2016·Granted Nov 14, 2017·12 cites·19 claims
- 2096US8629048B1Methods of forming a pattern on a substrateSIPANI VISHAL·Filed 2012·Granted Jan 14, 2014·32 cites·28 claims
- 2195US10964706B2Three-dimensional semiconductor device including integrated circuit, transistors and transistor components and method of fabricationTOKYO ELECTRON LTD·Filed 2019·Granted Mar 30, 2021·9 cites·10 claims
- 2295US10714391B2Method for controlling transistor delay of nanowire or nanosheet transistor devicesTOKYO ELECTRON LTD·Filed 2018·Granted Jul 14, 2020·11 cites·16 claims
- 2395US8871646B2Methods of forming a masking pattern for integrated circuitsMICRON TECHNOLOGY INC·Filed 2013·Granted Oct 28, 2014·19 cites·16 claims
- 2494US10453692B2Location-specific tuning of stress to control bow to control overlay in semiconductor processingTOKYO ELECTRON LTD·Filed 2017·Granted Oct 22, 2019·9 cites·20 claims
- 2594US10431468B2Location-specific tuning of stress to control bow to control overlay in semiconductor processingTOKYO ELECTRON LTD·Filed 2017·Granted Oct 1, 2019·8 cites·19 claims
- 2694US9240329B2Method for multiplying pattern density by crossing multiple patterned layersTOKYO ELECTRON LTD·Filed 2015·Granted Jan 19, 2016·11 cites·20 claims
- 2794US8273634B2Methods of fabricating substratesSILLS SCOTT·Filed 2008·Granted Sep 25, 2012·21 cites·37 claims
- 2893US11848236B2Method for recessing a fill material within openings formed on a patterned substrateTOKYO ELECTRON LTD·Filed 2021·Granted Dec 19, 2023·2 cites·20 claims
- 2993US10622233B2Amelioration of global wafer distortion based on determination of localized distortions of a semiconductor waferTOKYO ELECTRON LTD·Filed 2018·Granted Apr 14, 2020·14 cites·20 claims
- 3093US10475657B2Location-specific tuning of stress to control bow to control overlay in semiconductor processingTOKYO ELECTRON LTD·Filed 2017·Granted Nov 12, 2019·6 cites·20 claims
- 3193US10157747B2Location-specific tuning of stress to control bow to control overlay in semiconductor processingTOKYO ELECTRON LTD·Filed 2017·Granted Dec 18, 2018·6 cites·14 claims
- 3293US9760008B2Direct current superposition freezeTOKYO ELECTRON LTD·Filed 2014·Granted Sep 12, 2017·8 cites·21 claims
- 3393US9718082B2Inline dispense capacitorTOKYO ELECTRON LTD·Filed 2015·Granted Aug 1, 2017·12 cites·19 claims
- 3493US8815752B2Methods of forming features in semiconductor device structuresMICRON TECHNOLOGY INC·Filed 2012·Granted Aug 26, 2014·10 cites·22 claims
- 3593US8796155B2Methods of fabricating substratesSILLS SCOTT·Filed 2008·Granted Aug 5, 2014·20 cites·35 claims
- 3693US8492282B2Methods of forming a masking pattern for integrated circuitsDEVILLIERS ANTON·Filed 2009·Granted Jul 23, 2013·19 cites·31 claims
- 3793US8247302B2Methods of fabricating substratesSILLS SCOTT·Filed 2008·Granted Aug 21, 2012·19 cites·37 claims
- 3892US11114381B2Power distribution network for 3D logic and memoryTOKYO ELECTRON LTD·Filed 2019·Granted Sep 7, 2021·7 cites·20 claims
- 3992US10930764B2Extension region for a semiconductor deviceTOKYO ELECTRON LTD·Filed 2019·Granted Feb 23, 2021·6 cites·20 claims
- 4092US9824894B2Method for correcting wafer bow from overlayTOKYO ELECTRON LTD·Filed 2015·Granted Nov 21, 2017·8 cites·19 claims
- 4192US8575032B2Methods of forming a pattern on a substrateLIGHT SCOTT L·Filed 2011·Granted Nov 5, 2013·16 cites·35 claims
- 4291US11682559B2Method to form narrow slot contactsTOKYO ELECTRON LTD·Filed 2021·Granted Jun 20, 2023·2 cites·20 claims
- 4391US11488947B2Highly regular logic design for efficient 3D integrationTOKYO ELECTRON LTD·Filed 2020·Granted Nov 1, 2022·2 cites·17 claims
- 4490US11342427B23D directed self-assembly for nanostructuresTOKYO ELECTRON LTD·Filed 2020·Granted May 24, 2022·2 cites·20 claims
- 4590US10551743B2Critical dimension control by use of photo-sensitized chemicals or photo-sensitized chemically amplified resistTOKYO ELECTRON LTD·Filed 2017·Granted Feb 4, 2020·4 cites·26 claims
- 4690US9721793B2Method of patterning without dummy gatesTOKYO ELECTRON LTD·Filed 2016·Granted Aug 1, 2017·6 cites·14 claims
- 4790US9645391B2Substrate tuning system and method using optical projectionTOKYO ELECTRON LTD·Filed 2015·Granted May 9, 2017·6 cites·19 claims
- 4890US8450776B2Epitaxial devicesDEVILLIERS ANTON·Filed 2012·Granted May 28, 2013·7 cites·22 claims
- 4989US12336274B2Self-aligned method for vertical recess for 3D device integrationTOKYO ELECTRON LTD·Filed 2022·Granted Jun 17, 2025·1 cites·20 claims
- 5089US11264289B2Method for threshold voltage tuning through selective deposition of high-K metal gate (HKMG) film stacksTOKYO ELECTRON LTD·Filed 2020·Granted Mar 1, 2022·2 cites·19 claims
Showing the top 50 of 231 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →