Inventor · disambiguated record
Andrey Freidlin
Also filed as: FREIDLIN ANDREY
3 granted patents·2 citations·filing 2015–2017
50Inventor score
Technology areasG06F
Files withCADENCE DESIGN SYSTEMS INC3
Top patents by PatentIndex Score
3 records- 0161US10216888B2Constraint validation processCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Feb 26, 2019·2 cites·16 claims
- 0239US10909301B2Method and apparatus for determining waiver applicability conditions and applying the conditions to multiple errors or warnings in physical verification toolsCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Feb 2, 2021·0 cites·20 claims
- 0325US10210301B2System and method for implementing and validating star routing for power connections at chip levelCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Feb 19, 2019·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →