Inventor · disambiguated record
Anant Vithal Nori
Also filed as: NORI ANANT · NORI ANANT V · NORI ANANT VITHAL
28 granted patents·9 pending applications·30 citations·filing 2013–2024
93Inventor score
Top patents by PatentIndex Score
37 records- 0195US11575504B2Cryptographic computing engine for memory load and store units of a microarchitecture pipelineINTEL CORP·Filed 2020·Granted Feb 7, 2023·5 cites·25 claims
- 0290US11972126B2Data relocation for inline metadataINTEL CORP·Filed 2021·Granted Apr 30, 2024·2 cites·25 claims
- 0380US11874773B2Apparatuses, methods, and systems for dual spatial pattern prefetcherINTEL CORP·Filed 2019·Granted Jan 16, 2024·3 cites·24 claims
- 0480US10776270B2Memory-efficient last level cache architectureINTEL CORP·Filed 2018·Granted Sep 15, 2020·2 cites·21 claims
- 0578US10162756B2Memory-efficient last level cache architectureINTEL CORP·Filed 2017·Granted Dec 25, 2018·2 cites·17 claims
- 0677US9921839B1Coordinated thread criticality-aware memory schedulingSUBRAMANIAN LAVANYA·Filed 2016·Granted Mar 20, 2018·5 cites·22 claims
- 0776US10846084B2Supporting timely and context triggered prefetching in microprocessorsINTEL CORP·Filed 2018·Granted Nov 24, 2020·2 cites·20 claims
- 0874US12216581B2System, method, and apparatus for enhanced pointer identification and prefetchingINTEL CORP·Filed 2023·Granted Feb 4, 2025·0 cites·20 claims
- 0974US11847053B2Apparatuses, methods, and systems for a duplication resistant on-die irregular data prefetcherINTEL CORP·Filed 2020·Granted Dec 19, 2023·1 cites·24 claims
- 1072US9418013B2Selective prefetching for a sectored cacheANANTARAMAN ARAVINDH V·Filed 2014·Granted Aug 16, 2016·4 cites·20 claims
- 1171US8959266B1Dynamic priority control based on latency toleranceBONEN NADAV·Filed 2013·Granted Feb 17, 2015·3 cites·17 claims
- 1269US10713053B2Adaptive spatial access prefetcher apparatus and methodINTEL CORP·Filed 2018·Granted Jul 14, 2020·1 cites·18 claims
- 1366US11693780B2System, method, and apparatus for enhanced pointer identification and prefetchingINTEL CORP·Filed 2021·Granted Jul 4, 2023·0 cites·18 claims
- 1464US12505043B1Methods and apparatus for timed hardware delay for reductions in instruction fetch trafficINTEL CORP·Filed 2024·Granted Dec 23, 2025·0 cites·20 claims
- 1558US12417182B2De-prioritizing speculative code lines in on-chip cachesINTEL CORP·Filed 2021·Granted Sep 16, 2025·0 cites·21 claims
- 1658US11080194B2System, method, and apparatus for enhanced pointer identification and prefetchingINTEL CORP·Filed 2018·Granted Aug 3, 2021·0 cites·24 claims
- 1758US2021056030A1Multi-level system memory with near memory capable of storing compressed cache linesINTEL CORP·Filed 2020·Application pending·0 cites
- 1857US12360768B2Throttling code fetch for speculative code pathsINTEL CORP·Filed 2021·Granted Jul 15, 2025·0 cites·18 claims
- 1955US12405890B2Method and apparatus for leveraging simultaneous multithreading for bulk compute operationsINTEL CORP·Filed 2021·Granted Sep 2, 2025·0 cites·24 claims
- 2054US11941534B2Genome sequence alignment system and methodINTEL CORP·Filed 2019·Granted Mar 26, 2024·0 cites·20 claims
- 2154US10635593B2Create page locality in cache controller cache allocationINTEL CORP·Filed 2017·Granted Apr 28, 2020·0 cites·18 claims
- 2253US12468631B2Region aware delta prefetcherINTEL CORP·Filed 2021·Granted Nov 11, 2025·0 cites·25 claims
- 2353US12112171B2Loop support extensionsINTEL CORP·Filed 2020·Granted Oct 8, 2024·0 cites·17 claims
- 2452US11188467B2Multi-level system memory with near memory capable of storing compressed cache linesINTEL CORP·Filed 2017·Granted Nov 30, 2021·0 cites·12 claims
- 2552US2025103509A1Microarchitecture and instruction set architecture extensions for efficient iso-area victim buffering through translation lookaside buffer partitioningINTEL CORP·Filed 2023·Application pending·0 cites
- 2652US2025298622A1Circuitry and methods for early fetch of call instructionsINTEL CORP·Filed 2024·Application pending·0 cites
- 2751US10956327B2Systems and methods for mitigating dram cache conflicts through hardware assisted redirection of pages (HARP)INTEL CORP·Filed 2019·Granted Mar 23, 2021·0 cites·15 claims
- 2851US2025004766A1Software splitting for software defined coresGAUR JAYESH·Filed 2024·Application pending·0 cites
- 2950US9846648B2Create page locality in cache controller cache allocationINTEL CORP·Filed 2015·Granted Dec 19, 2017·0 cites·22 claims
- 3048US12066945B2Dynamic shared cache partition for workload with large code footprintINTEL CORP·Filed 2020·Granted Aug 20, 2024·0 cites·18 claims
- 3148US2024211408A1Apparatus and method for probabilistic cache replacement for accelerating address translationINTEL CORP·Filed 2022·Application pending·0 cites
- 3248US2025217211A1Software defined super coresGAUR JAYESH·Filed 2023·Application pending·0 cites
- 3344US2025217143A1Software defined super coresGAUR JAYESH·Filed 2023·Application pending·0 cites
- 3440US10559348B2System, apparatus and method for simultaneous read and precharge of a memoryINTEL CORP·Filed 2018·Granted Feb 11, 2020·0 cites·20 claims
- 3540US9767041B2Managing sectored cacheINTEL CORP·Filed 2015·Granted Sep 19, 2017·0 cites·12 claims
- 3639US2020285580A1Speculative memory activationINTEL CORP·Filed 2017·Application pending·0 cites
- 3735US2018173637A1Efficient memory aware cache managementINTEL CORP·Filed 2016·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →