Multi-level system memory with near memory capable of storing compressed cache lines

Abstract

A method is described. The method includes receiving a read or write request for a cache line. The method includes directing the request to a set of logical super lines based on the cache line's system memory address. The method includes associating the request with a cache line of the set of logical super lines. The method includes, if the request is a write request: compressing the cache line to form a compressed cache line, breaking the cache line down into smaller data units and storing the smaller data units into a memory side cache. The method includes, if the request is a read request: reading smaller data units of the compressed cache line from the memory side cache and decompressing the cache line.

What is claimed is: 
     
         1 . An apparatus, comprising:
 processor logic circuitry to execute program code;   a multi-level memory comprising a first level of memory and a second level of memory, the first level of memory having lower access times than the second level of memory, the first level of memory being composed of a different type of memory technology than the second level of memory, the first level of memory being integrated on a same semiconductor chip as the processor logic circuitry, the second level of memory residing outside the semiconductor chip that the processor logic circuitry and the first level of memory are integrated on, the second level of memory being composed of dynamic random access memory (DRAM), wherein, the first level of memory is to have a first portion that is to function as a cache for the processor logic circuitry and a second portion that is to have a region of address space that is addressable by the program code, and wherein, the second level of memory is also addressable by the program code; and,   compression circuitry to compress data items that are entered into the first level of memory to enhance the first level of memory's memory capacity, the compression circuitry designed to compress two lines of data into one line of data.   
     
     
         2 . The apparatus of  claim 1  wherein the first level of memory is composed of SRAM. 
     
     
         3 . The apparatus of  claim 1  wherein the compression circuitry is designed to compress to at least one compression ratio other than 2:1. 
     
     
         4 . The apparatus of  claim 3  wherein the compression circuitry is designed to compress at a ratio of 4:1. 
     
     
         5 . The apparatus of  claim 1  wherein the first and second levels of memory are capable of storing graphics information. 
     
     
         6 . An apparatus, comprising:
 processor logic circuitry to execute program code;   a controller to control a multi-level memory comprising a first level of memory and a second level of memory, the first level of memory having lower access times than the second level of memory, the first level of memory being composed of a different type of memory technology than the second level of memory, the first level of memory being integrated on a same semiconductor chip as the processor logic circuitry, the second level of memory residing outside the semiconductor chip that the processor logic circuitry and the first level of memory are integrated on, the second level of memory being composed of dynamic random access memory (DRAM), wherein, the first level of memory is to have a first portion that is to function as a cache for the processor logic circuitry and a second portion that is to have a region of address space that is addressable by the program code, and wherein, the second level of memory is also addressable by the program code; and,   compression circuitry to compress data items that are entered into the first level of memory to enhance the first level of memory's memory capacity, the compression circuitry designed to compress two lines of data into one line of data.   
     
     
         7 . The apparatus of  claim 6  wherein the first level of memory is composed of SRAM. 
     
     
         8 . The apparatus of  claim 6  wherein the compression circuitry is designed to compress to at least one compression ratio other than 2:1. 
     
     
         9 . The apparatus of  claim 8  wherein the compression circuitry is designed to compress at a ratio of 4:1. 
     
     
         10 . The apparatus of  claim 6  wherein the first and second levels of memory are capable of storing graphics information. 
     
     
         11 . A method, comprising:
 executing program code with processor logic circuitry;   controlling a multi-level memory comprising a first level of memory and a second level of memory, the first level of memory having lower access times than the second level of memory, the first level of memory being composed of a different type of memory technology than the second level of memory, the first level of memory being integrated on a same semiconductor chip as the processor logic circuitry, the second level of memory residing outside the semiconductor chip that the processor logic circuitry and the first level of memory are integrated on, the second level of memory being composed of dynamic random access memory (DRAM), wherein, the first level of memory has a first portion that functions as a cache for the processor logic circuitry and a second portion that has a region of address space that is addressable by the executing program code, and wherein, the second level of memory is also addressable by the executing program code; and,   compressing data items that are entered into the first level of memory to enhance the first level of memory's memory capacity, the compressing comprising compressing two lines of data into one line of data.   
     
     
         12 . The method of  claim 11  wherein the first level of memory is composed of SRAM. 
     
     
         13 . The method of  claim 11  wherein the compression circuitry is designed to compress to at least one compression ratio other than 2:1. 
     
     
         14 . The method of  claim 13  wherein the compression circuitry is designed to compress at a ratio of 4:1. 
     
     
         15 . The method of  claim 11  wherein the first and second levels of memory are capable of storing graphics information.