Inventor · disambiguated record
Jayesh Gaur
Also filed as: GAUR JAYESH
30 granted patents·30 pending applications·42 citations·filing 2011–2024
94Inventor score
Top patents by PatentIndex Score
60 records- 0195US11575504B2Cryptographic computing engine for memory load and store units of a microarchitecture pipelineINTEL CORP·Filed 2020·Granted Feb 7, 2023·5 cites·25 claims
- 0293US12028094B2Application programming interface for fine grained low latency decompression within processor coreINTEL CORP·Filed 2020·Granted Jul 2, 2024·3 cites·24 claims
- 0390US11972126B2Data relocation for inline metadataINTEL CORP·Filed 2021·Granted Apr 30, 2024·2 cites·25 claims
- 0489US12086591B2Device, method and system to predict an address collision by a load and a storeINTEL CORP·Filed 2021·Granted Sep 10, 2024·3 cites·20 claims
- 0588US10915421B1Technology for dynamically tuning processor featuresINTEL CORP·Filed 2019·Granted Feb 9, 2021·4 cites·20 claims
- 0682US10496413B2Efficient hardware-based extraction of program instructions for critical pathsINTEL CORP·Filed 2017·Granted Dec 3, 2019·4 cites·22 claims
- 0780US10776270B2Memory-efficient last level cache architectureINTEL CORP·Filed 2018·Granted Sep 15, 2020·2 cites·21 claims
- 0879US10176099B2Using data pattern to mark cache lines as invalidINTEL CORP·Filed 2016·Granted Jan 8, 2019·3 cites·21 claims
- 0978US10162756B2Memory-efficient last level cache architectureINTEL CORP·Filed 2017·Granted Dec 25, 2018·2 cites·17 claims
- 1076US10268600B2System, apparatus and method for prefetch-aware replacement in a cache memory hierarchy of a processorINTEL CORP·Filed 2017·Granted Apr 23, 2019·3 cites·20 claims
- 1175US10754655B2Automatic predication of hard-to-predict convergent branchesINTEL CORP·Filed 2018·Granted Aug 25, 2020·2 cites·18 claims
- 1275US10331582B2Write congestion aware bypass for non-volatile memory, last level cache (LLC) dropping from write queue responsive to write queue being full and read queue threshold wherein the threshold is derived from latency of write to LLC and main memory retrieval timeINTEL CORP·Filed 2017·Granted Jun 25, 2019·2 cites·20 claims
- 1375US2025117329A1Instruction and Micro-Architecture Support for Decompression on CoreINTEL CORP·Filed 2024·Application pending·0 cites
- 1471US11656971B2Technology for dynamically tuning processor featuresINTEL CORP·Filed 2022·Granted May 23, 2023·0 cites·20 claims
- 1569US10719355B2Criticality based port schedulingINTEL CORP·Filed 2018·Granted Jul 21, 2020·1 cites·20 claims
- 1668US10013352B2Partner-aware virtual microsectoring for sectored cache architecturesINTEL CORP·Filed 2014·Granted Jul 3, 2018·3 cites·17 claims
- 1767US11256599B2Technology for dynamically tuning processor featuresINTEL CORP·Filed 2020·Granted Feb 22, 2022·0 cites·20 claims
- 1866US12182018B2Instruction and micro-architecture support for decompression on coreINTEL CORP·Filed 2020·Granted Dec 31, 2024·0 cites·25 claims
- 1966US10866902B2Memory aware reordered sourceINTEL CORP·Filed 2016·Granted Dec 15, 2020·1 cites·25 claims
- 2059US11645078B2Detecting a dynamic control flow re-convergence point for conditional branches in hardwareINTEL CORP·Filed 2019·Granted May 9, 2023·0 cites·24 claims
- 2159US8667222B2Bypass and insertion algorithms for exclusive last-level cachesGAUR JAYESH·Filed 2011·Granted Mar 4, 2014·2 cites·18 claims
- 2258US2021056030A1Multi-level system memory with near memory capable of storing compressed cache linesINTEL CORP·Filed 2020·Application pending·0 cites
- 2357US2025298623A1Bandwidth aware simultaneous multi-threadingINTEL CORP·Filed 2024·Application pending·0 cites
- 2456US2025217155A1Early resteering of mispredicted branchesINTEL CORP·Filed 2023·Application pending·0 cites
- 2554US2025217288A1Register renaming cachingINTEL CORP·Filed 2023·Application pending·0 cites
- 2653US2025217160A1Software defined super coresINTEL CORP·Filed 2023·Application pending·0 cites
- 2752US12430135B2Device, method, and system to facilitate improved bandwidth of a branch prediction unitINTEL CORP·Filed 2021·Granted Sep 30, 2025·0 cites·20 claims
- 2852US11188467B2Multi-level system memory with near memory capable of storing compressed cache linesINTEL CORP·Filed 2017·Granted Nov 30, 2021·0 cites·12 claims
- 2952US10846093B2System, apparatus and method for focused data value prediction to accelerate focused instructionsINTEL CORP·Filed 2018·Granted Nov 24, 2020·0 cites·20 claims
- 3052US2025217157A1Software defined super coresINTEL CORP·Filed 2023·Application pending·0 cites
- 3151US10956327B2Systems and methods for mitigating dram cache conflicts through hardware assisted redirection of pages (HARP)INTEL CORP·Filed 2019·Granted Mar 23, 2021·0 cites·15 claims
- 3251US9251096B2Data compression in processor cachesINTEL CORP·Filed 2013·Granted Feb 2, 2016·0 cites·20 claims
- 3351US2024103878A1Short pipeline for fast recovery from a branch mispredictionINTEL CORP·Filed 2022·Application pending·0 cites
- 3451US2025004766A1Software splitting for software defined coresGAUR JAYESH·Filed 2024·Application pending·0 cites
- 3550US2024103874A1Instruction elimination through hardware driven memoization of loop instancesINTEL CORP·Filed 2022·Application pending·0 cites
- 3649US12020033B2Apparatus and method for hardware-based memoization of function calls to reduce instruction executionINTEL CORP·Filed 2020·Granted Jun 25, 2024·0 cites·25 claims
- 3748US2023195456A1System, apparatus and method for throttling fusion of micro-operations in a processorINTEL CORP·Filed 2021·Application pending·0 cites
- 3848US2025217211A1Software defined super coresGAUR JAYESH·Filed 2023·Application pending·0 cites
- 3948US2025199813A1Apparatus and method for profile-optimized loopsINTEL CORP·Filed 2023·Application pending·0 cites
- 4047US12130738B2Compressed cache memory with decompress on faultINTEL CORP·Filed 2020·Granted Oct 29, 2024·0 cites·18 claims
- 4147US2025165255A1Handling clears in software defined super coresGAUR JAYESH·Filed 2024·Application pending·0 cites
- 4247US2025217158A1Software defined super coresGAUR JAYESH·Filed 2023·Application pending·0 cites
- 4345US9720829B2Online learning based algorithms to increase retention and reuse of GPU-generated dynamic surfaces in outer-level cachesSRINIVASAN SURESH·Filed 2011·Granted Aug 1, 2017·0 cites·20 claims
- 4445US2025217146A1Software defined super coresGAUR JAYESH·Filed 2023·Application pending·0 cites
- 4545US2025217144A1Software defined super coresGAUR JAYESH·Filed 2023·Application pending·0 cites
- 4645US2023195465A1Device, method and system to provide a predicted value with a sequence of micro-operationsINTEL CORP·Filed 2021·Application pending·0 cites
- 4745US2025217154A1Software defined super coresGAUR JAYESH·Filed 2023·Application pending·0 cites
- 4844US2025217143A1Software defined super coresGAUR JAYESH·Filed 2023·Application pending·0 cites
- 4944US2022197643A1Speculative decompression within processor core cachesINTEL CORP·Filed 2020·Application pending·0 cites
- 5044US2022197813A1Application programming interface for fine grained low latency decompression within processor coreINTEL CORP·Filed 2020·Application pending·0 cites
Showing the top 50 of 60 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →