Inventor · disambiguated record
Zvika Greenfield
Also filed as: GREENFIELD ZVIKA
29 granted patents·6 pending applications·642 citations·filing 2009–2020
96Inventor score
Top patents by PatentIndex Score
35 records- 0199US10210925B2Row hammer refresh commandINTEL CORP·Filed 2017·Granted Feb 19, 2019·75 cites·20 claims
- 0299US9865326B2Row hammer refresh commandINTEL CORP·Filed 2016·Granted Jan 9, 2018·83 cites·42 claims
- 0399US9747971B2Row hammer refresh commandINTEL CORP·Filed 2015·Granted Aug 29, 2017·84 cites·46 claims
- 0499US9236110B2Row hammer refresh commandBAINS KULJIT S·Filed 2012·Granted Jan 12, 2016·65 cites·30 claims
- 0598US9117544B2Row hammer refresh commandBAINS KULJIT·Filed 2013·Granted Aug 25, 2015·103 cites·15 claims
- 0696US9251885B2Throttling support for row-hammer countersINTEL CORP·Filed 2012·Granted Feb 2, 2016·68 cites·24 claims
- 0796US8938573B2Row hammer condition monitoringGREENFIELD ZVIKA·Filed 2012·Granted Jan 20, 2015·88 cites·14 claims
- 0890US9026725B2Training for command/address/control/clock delays under uncertain initial conditions and for mapping swizzled data to command/address signalsINTEL CORP·Filed 2012·Granted May 5, 2015·20 cites·21 claims
- 0986US9076019B2Method and apparatus for memory encryption with integrity check and protection against replay attacksGUERON SHAY·Filed 2011·Granted Jul 7, 2015·9 cites·20 claims
- 1084US9734079B2Hybrid exclusive multi-level memory architecture with memory managementINTEL CORP·Filed 2013·Granted Aug 15, 2017·9 cites·27 claims
- 1181US11036412B2Dynamically changing between latency-focused read operation and bandwidth-focused read operationINTEL CORP·Filed 2019·Granted Jun 15, 2021·3 cites·17 claims
- 1281US9009540B2Memory subsystem command bus stress testingMOZAK CHRISTOPHER P·Filed 2012·Granted Apr 14, 2015·8 cites·30 claims
- 1379US10176099B2Using data pattern to mark cache lines as invalidINTEL CORP·Filed 2016·Granted Jan 8, 2019·3 cites·21 claims
- 1473US10204047B2Memory controller for multi-level system memory with coherency unitINTEL CORP·Filed 2015·Granted Feb 12, 2019·2 cites·27 claims
- 1572US9418013B2Selective prefetching for a sectored cacheANANTARAMAN ARAVINDH V·Filed 2014·Granted Aug 16, 2016·4 cites·20 claims
- 1672US8868992B2Robust memory link testing using memory controllerSPRY BRYAN L·Filed 2009·Granted Oct 21, 2014·10 cites·13 claims
- 1771US8959266B1Dynamic priority control based on latency toleranceBONEN NADAV·Filed 2013·Granted Feb 17, 2015·3 cites·17 claims
- 1866US9030903B2Method, apparatus and system for providing a memory refreshBAINS KULJIT S·Filed 2012·Granted May 12, 2015·3 cites·26 claims
- 1965US9582430B2Asymmetric set combined cacheINTEL CORP·Filed 2015·Granted Feb 28, 2017·1 cites·24 claims
- 2062US9424198B2Method, system and apparatus including logic to manage multiple memories as a unified exclusive memoryINTEL CORP·Filed 2012·Granted Aug 23, 2016·1 cites·19 claims
- 2159US10657058B2Interleaved cache controllers with shared metadata and related devices and systemsINTEL CORP·Filed 2018·Granted May 19, 2020·0 cites·24 claims
- 2258US2021056030A1Multi-level system memory with near memory capable of storing compressed cache linesINTEL CORP·Filed 2020·Application pending·0 cites
- 2353US10949356B2Fast page fault handling process implemented on persistent memoryINTEL CORP·Filed 2019·Granted Mar 16, 2021·0 cites·20 claims
- 2452US11188467B2Multi-level system memory with near memory capable of storing compressed cache linesINTEL CORP·Filed 2017·Granted Nov 30, 2021·0 cites·12 claims
- 2550US10558570B2Concurrent accesses of asymmetrical memory sourcesINTEL CORP·Filed 2017·Granted Feb 11, 2020·0 cites·16 claims
- 2650US2017329711A1Interleaved cache controllers with shared metadata and related devices and systemsINTEL CORP·Filed 2016·Application pending·0 cites
- 2748US10241916B2Sparse superline removalINTEL CORP·Filed 2017·Granted Mar 26, 2019·0 cites·21 claims
- 2847US10915453B2Multi level system memory having different caching structures and memory controller that supports concurrent look-up into the different caching structuresINTEL CORP·Filed 2016·Granted Feb 9, 2021·0 cites·18 claims
- 2945US10304418B2Operating system transparent system memory abandonmentINTEL CORP·Filed 2016·Granted May 28, 2019·0 cites·12 claims
- 3042US2019102314A1Tag cache adaptive power gatingINTEL CORP·Filed 2017·Application pending·0 cites
- 3140US9767041B2Managing sectored cacheINTEL CORP·Filed 2015·Granted Sep 19, 2017·0 cites·12 claims
- 3240US2020226066A1Apparatus and method for efficient management of multi-level memoryINTEL CORP·Filed 2020·Application pending·0 cites
- 3339US10678706B2Cache memory with scrubber logicINTEL CORP·Filed 2018·Granted Jun 9, 2020·0 cites·18 claims
- 3434US2017091099A1Memory controller for multi-level system memory having sectored cacheGREENFIELD ZVIKA·Filed 2015·Application pending·0 cites
- 3533US2014085995A1Method, apparatus and system for determining a count of accesses to a row of memoryGREENFIELD ZVIKA·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →